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LT1940

1940i

BLOCK DIAGRA

is also clamped to the RUN/SS pin voltage. As the internal

current source charges the external soft-start capacitor,

the current limit increases slowly.

Each switcher contains an independent oscillator. This

slave oscillator is normally synchronized to the master

oscillator. However, during start-up, short-circuit or over-

load conditions, the FB pin voltage will be near zero and an

internal comparator gates the master oscillator clock

signal. This allows the slave oscillator to run the regulator

at a lower frequency. This frequency foldback behavior

helps to limit switch current and power dissipation under

fault conditions.

The switch driver operates from either the input or from

the BOOST pin. An external capacitor and diode are used

to generate a voltage at the BOOST pin that is higher than

the input supply. This allows the driver to fully saturate the

internal bipolar NPN power switch for efficient operation.

A power good comparator trips when the FB pin is at 90%

of its regulated value. The PG output is an open collector

transistor that is off when the output is in regulation,

allowing an external resistor to pull the PG pin high. Power

good is valid when the LT1940 is enabled (either RUN/SS

pin is high) and VIN is greater than ~2.4V.

The master oscillator generates two clock signals of

opposite phase.

The two switchers are current mode step-down regula-

tors. This means that instead of directly modulating the

duty cycle of the power switch, the feedback loop controls

the peak current in the switch during each cycle. This

current mode control improves loop dynamics and pro-

vides cycle-by-cycle current limit.

The Block Diagram shows only one of the two switching

regulators. A pulse from the slave oscillator sets the RS

flip-flop and turns on the internal NPN bipolar power

switch. Current in the switch and the external inductor

begins to increase. When this current exceeds a level

determined by the voltage at VC, current comparator C1

resets the flip-flop, turning off the switch. The current in

the inductor flows through the external Schottky diode,

and begins to decrease. The cycle begins again at the next

pulse from the oscillator. In this way the voltage on the VC

pin controls the current through the inductor to the output.

The internal error amplifier regulates the output voltage by

continually adjusting the VC pin voltage.

The threshold for switching on the VC pin is 0.8V, and an

active clamp of 1.8V limits the output current. The VC pin

APPLICATIO S I FOR ATIO

FB Resistor Network

The output voltage is programmed with a resistor divider

between the output and the FB pin. Choose the 1%

resistors according to:

R1 = R2(VOUT/1.25 – 1)

R2 should be 10.0k

Ω or less to avoid bias current errors.

Reference designators refer to the Block Diagram in

Figure 2.

Input Voltage Range

The minimum input voltage is determined by either the

LT1940’s minimum operating voltage of ~3.5V, or by its

maximum duty cycle. The duty cycle is the fraction of time

that the internal switch is on and is determined by the input

and output voltages:

DC = (VOUT + VD)/(VIN – VSW + VD)

where VD is the forward voltage drop of the catch diode

(~0.4V) and VSW is the voltage drop of the internal switch

(~0.3V at maximum load). This leads to a minimum input

voltage of:

VINMIN = (VOUT + VD)/DCMAX - VD + VSW

with DCMAX = 0.78.

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