AX88796 datasheet(65/71 Pages) ASIX

65 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

Errata of AX88796

1. MII Station Management functions has some defference from previous target

specification.

Description: The target specification is using station management can access both

internal PHY registers and external PHY registers when the PHY address is matched

as describe in section 5.5. Anyway, this version can only access the current selected

PHY’s registers. How do you know which is the selected media or PHY? Please refer

to section 4.1.16 GPO and Control (GPOC) register.

Solution: The defect will not affect single media application that is using embedded

PHY. When using MII interface connects to external media (for example HomePNA)

to come out with combo solution. Care must be taken, be sure which media is the

current selected when you access PHY registers.

2. AX88796 can’t support 68K CPU with byte mode

Solution: Please using word mode for high performance. MC68008 has only 8-bit bus, so

AX88796 can’t support this CPU.

3. When AX88796 transmit a packet and the packet is collided for 16 times. The packet

will be reported as as PTX bit asserted rather than TXE asserted.

Solution: Packet collided 16 times and aborted is normal way, even that is rare happen

in live network, in very heavy traffic. While the upper protocol layer will handle the

situation and cover the packet loss.

AX88796 Datasheet(PDF) 65 Page - ASIX Electronics Corporation