TLF5947

February 1988

CD4014BMCD4014BC 8-Stage Static Shift Register

General Description

The CD4014BMCD4014BC is an 8-stage parallel inputse-

rial output shift register A parallelserial control input en-

ables individual JAM inputs to each of 8 stages Q outputs

are available from the sixth seventh and eighth stages All

outputs have equal source and sink current capabilities and

conform to standard ‘‘B’’ series output drive

When the parallelserial control input is in the logical ‘‘0’’

state data is serially shifted into the register synchronously

with the positive transition of the clock When the parallel

serial control input is in the logical ‘‘1’’ state data is jammed

into each stage of the register synchronously with the posi-

tive transition of the clock

All inputs are protected against static discharge with diodes

Features

Y

Wide supply voltage range

30V to 15V

Y

High noise immunity

Y

Low power TTL

Fan out of 2 driving 74L

compatibility

or 1 driving 74LS

Y

5V – 10V – 15V parametric ratings

Y

Symmetrical output characteristics

Y

Maximum input leakage

1 mA at 15V over full temperature range

Connection Diagram

Dual-In-Line Package

TLF5947 – 1

Top View

Truth Table

Serial

Parallel

Q1

CL

Input

Serial

PI 1 PI n

(Internal)

Control

L

X1

0

0

0

0

L

X1

1

0

1

0

L

X1

0

1

0

1

L

X1

1

1

1

1

L

00

X

X

0

L

10

X

X

1

K

X

X

X

X

Q1

No Change

Level change

Order Number CD4014B

Logic Diagram

TLF5947 – 2

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A