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CD4015BC Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CD4015BC Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page ![]() TLF5948 June 1996 CD4015BMCD4015BC Dual 4-Bit Static Shift Register General Description The CD4015BMCD4015BC contains two identical 4-stage serial-inputparallel-output registers with independent ‘‘Data’’ ‘‘Clock’’ and ‘‘Reset’’ inputs The logic level pres- ent at the input of each stage is transferred to the output of that stage at each positive-going clock transition A logic high on the ‘‘Reset’’ input resets all four stages covered by that input All inputs are protected from static discharge by a series resistor and diode clamps to VDD and VSS Features Y Wide supply voltage range 30V to 18V Y High noise immunity 045 VDD (typ) Y Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Y Medium speed operation 8 MHz (typ) clock rate Y Fully static design VDD b VSS e 10V Applications Y Serial-inputparallel-output data queueing Y Serial to parallel data conversion Y General purpose register Connection Diagram and Truth Table Dual-In-Line Package TLF5948 – 1 CLU DRQ1 Qn L 00 0 Qnb1 L 10 1 Qnb1 K X0 Q1 Qn (No change) XX 1 0 0 U Level change X e Don’t care case Order Number CD4015B C1996 National Semiconductor Corporation RRD-B30M76Printed in U S A http www nationalcom |
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