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CD4031BC Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CD4031BC
Description  64-Stage Static Shift Register
PDF  6 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CD4031BC Datasheet(HTML) 4 Page - National Semiconductor (TI)

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AC Electrical Characteristics
TA e 25 C CL e 50 pF RL e 200k Input tr e tf e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL tPLH
Propagation Delay Time Clock to Q and Q
VCC e 5V
300
600
ns
VCC e 10V
125
250
ns
VCC e 15V
100
200
ns
tPHL tPLH
Propagation Delay Time Clock to CLD
VCC e 5V
125
250
ns
VCC e 10V
60
125
ns
VCC e 15V
50
100
ns
tTHL tTLH
Output Transition Time All Outputs
VCC e 5V
100
200
ns
VCC e 10V
50
100
ns
VCC e 15V
40
80
ns
tSU0
Minimum Data Setup Time DATA IN or
VCC e 5V
100
200
ns
tSU1
RECIRCULATE IN to Clock
VCC e 10V
50
100
ns
VCC e 15V
40
80
ns
tH0
Minimum Data Hold Time Clock to DATA IN
VCC e 5V
100
200
ns
tH1
or RECIRCULATE IN
VCC e 10V
50
100
ns
VCC e 15V
40
80
ns
tWL tWH
Minimum Clock Pulse Width
VCC e 5V
150
30
ns
VCC e 10V
60
125
ns
VCC e 15V
50
100
ns
fCL
Maximum Clock Frequency
VCC e 5V
16
32
MHz
VCC e 10V
40
80
MHz
VCC e 15V
50
10
MHz
tRCL tFCL
Maximum Clock Input Rise and Fall Times
VCC e 5V
15
m
s
(Note 4)
VCC e 10V
10
m
s
VCC e 15V
5
m
s
CIN
Input Capacitance
Any Input
5
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 4
When clocking cascaded packages in parallel one should insure that trCL s 2(tPD b tH) where tPD e the propagation delay of the driving stage
and tH e the hold time of the driven stage
Block Diagram
cascading packages using DELAYED CLOCK (CLD) output
TLF5962 – 4
4



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