AD6673 datasheet(34/45 Pages) AD

34 / 45 page

AD6673

Data Sheet

Rev. C | Page 34 of 45

Fast Threshold Detection (FDA and FDB)

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located in Register 0x47 and Register 0x48. The selected threshold

the ADC. The fast upper threshold detection has a latency of

4 clock cycles. The approximate upper threshold magnitude is

defined by

Upper Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/216)

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Register 0x49 and Register 0x4A. The fast

detect lower threshold register is a 16-bit register that is compared

with the signal magnitude at the output of the ADC. This com-

parison is subject to the ADC pipeline latency but is accurate in

terms of converter resolution. The lower threshold magnitude is

defined by

Lower Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/216)

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located in Register 0x4B and Register 0x4C.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 55.

UPPER THRESHOLD

LOWER THRESHOLD

FDA OR FDB

DWELL TIME

TIMER RESET BY

RISE ABOVE LT

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE LT

DWELL TIME

Figure 55. Threshold Settings for FDA and FDB Signals

AD6673 Datasheet(PDF) 34 Page - Analog Devices