Mar. 2002

13

ZC0301

VGA & CIF USB PC Camera Controller

Appendix I Sensor Interface Description

ZC0301 supports Hyundai VGA format sensors (HV7131B).

1.

INPUT / OUTPUT AC CHARACTERISTICS

All output timing delays are measured with output load 60pF

Output delay includes the internal clock path delay [6ns] and output driving delay that changes in respect to

the output load, the operating environments, and a board design.

Due to the variable valid time delay of the output, output signals may be latched in the negative edge of

MCLK for the stable data transfer between the image sensor and a host for less than 15MHz operation.

2.

MCLK TO HSYNC / VSYNC Timing

T1: MCLK RISING TO HSYNC/VSYNC valid maximum Time: 18ns [output load: 60pF]

T2: HSYNC/VSYNC valid Time: minimum 1 clock (subject to T1, T2 timing rule )

3.

MCLK to DATA Timing

T3: MCLK rising to DATA Valid maximum Time: 18ns [output load:60pF]

Note: HSYNC signal is high when valid data is on the DATA bus.

4.

ENB Timing