M02050 datasheet(2/2 Pages) MA-COM

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General Information: (949) 579-3000

Headquarters – Newport Beach

4000 MacArthur Blvd., East Tower

Newport Beach, CA 92660-3007

02050-BRF-001-A

logo are trademarks of Mindspeed Technologies. All other trademarks are the property

of their respective owners. Although Mindspeed Technologies strives for accuracy in all

its publications, this material may contain errors or omissions and is subject to change

without notice. This material is provided as is and without any express or implied

warranties, including merchantability, fitness for a particular purpose and

non-infringement. Mindspeed Technologies shall not be liable for any special, indirect,

incidental or consequential damages as a result of its use.

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• 2.5 Gbps STM-16/OC-48

SDH/SONET

• 1.06, 2.12 Gbps Fibre Channel

• 1.25 Gbps Ethernet

• 2.67 Gbps SDH/SONET with FEC

• Operates with a 3.3V (“-14”) or

3.3V/5V (“-15”) supply

• 4 mV maximum input sensitivity at

2.5 Gbps

• CML outputs

• Rate selection for ≤ 1.25 Gbps

operation

• Average receive power monitor

output (RSSIAVG)

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• M02050-14 3.3V supply

• M02050-15 3.3V/5.5V supply

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the input signal level is monitored by the level detector (which

also outputs the RSSIPP voltage). As described in the RSSIPP

section, this voltage is proportional to the input signal peak

to peak value. The voltage at STSET is internally compared to

the signal level from the level detector. When the level

detector voltage is less than V(STSET), LOS is asserted and

will stay asserted until the input signal level increases by a

predefined amount of hysteresis. When the input level

increases by more than this hysteresis above V(STSET), LOS is

de-asserted.

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-P

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r ((R

SIIPPPP))

The RSSIPP output voltage is logarithmically proportional to

the peak-to-peak level of the input signal. It is not necessary

to connect an external capacitor to this output. Internally, the

RSSI voltage is compared with a user selectable reference to

determine loss of signal as described in the previous section.

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When asserted, the active high power down (Jam) pin forces

the outputs to a logic “one” state. This ensures that no data

is propagated through the system. The loss of signal detec-

tion circuit can be used to automatically force the data

outputs to a high state when the input signal falls below the

threshold. The function is normally used to allow data to

propagate only when the signal is above the user's bit-error-

rate requirement. It, therefore, inhibits the data outputs

toggling due to noise when there is no signal present

(“squelch”). In order to implement this function, LOS should be

connected to the Jam pin, thus forcing the data outputs to a

logic “one” state when the signal falls below the threshold.

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r ((R

SIIAAVVGG))

The RSSIAVG output current is a mirrored version of the

RxAVGIN current from compatible TIAs. It sources rather than

sinks the current making it compatible with DDMI type inter-

faces.

Biasing

Jam

REF

RATESEL

Output

Buffer

Offset Cancel

Comparator

Vcc

LOS

RSSIPP

PECLN

PECLP

STSET

DINP

DINN

RxAVGIN

RSSIAVG

Level

Detector

Threshold

Setting

Circuit

Level

Shift

VTT

Limiting

Amplifier

M02050 Block Diagram

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