ADC0820 datasheet(11/22 Pages) NSC

11 / 22 page

1.0 Functional Description (Continued)

sured while WR is low. In RD mode, sampling occurs during

the first 800 ns of RD. Because of the input connections to

the ADC0820’s LS and MS comparators, the converter has

the ability to sample V

IN at one instant (Section 2.4), despite

the fact that two separate 4-bit conversions are being done.

More specifically, when WR is low the MS flash is in compare

mode (connected to V

IN), and the LS flash is in zero mode

(also connected to V

IN). Therefore both flash ADCs sample

IN at the same time.

1.4 DIGITAL INTERFACE

The ADC0820 has two basic interface modes which are se-

lected by strapping the MODE pin high or low.

RD Mode

With the MODE pin grounded, the converter is set to Read

mode. In this configuration, a complete conversion is done

by pulling RD low until output data appears. An INT line is

provided which goes low at the end of the conversion as well

as a RDY output which can be used to signal a processor

that the converter is busy or can also serve as a system

Transfer Acknowledge signal.

When in RD mode, the comparator phases are internally trig-

gered. At the falling edge of RD, the MS flash converter goes

from zero to compare mode and the LS ADC’s comparators

enter their zero cycle. After 800 ns, data from the MS flash is

latched and the LS flash ADC enters compare mode. Follow-

ing another 800 ns, the lower 4 bits are recovered.

WR then RD Mode

With the MODE pin tied high, the A/D will be set up for the

WR-RD mode. Here, a conversion is started with the WR in-

put; however, there are two options for reading the output

data which relate to interface timing. If an interrupt driven

scheme is desired, the user can wait for INT to go low before

reading the conversion result (

Figure 10 ). INT will typically

go low 800 ns after WR’s rising edge. However, if a shorter

conversion time is desired, the processor need not wait for

INT and can exercise a read after only 600 ns (

Figure 9 ). If

this is done, INT will immediately go low and data will appear

at the outputs.

Stand-Alone

For stand-alone operation in WR-RD mode, CS and RD can

be tied low and a conversion can be started with WR. Data

will be valid approximately 800 ns following WR’s rising

edge.

RD Mode (Pin 7 is Low)

DS005501-16

DS005501-17

FIGURE 9. WR-RD Mode (Pin 7 is High and t

RD<tI)

DS005501-18

FIGURE 10. WR-RD Mode (Pin 7 is High and t

RD>tI)

WR-RD Mode (Pin 7 is High) Stand-Alone Operation

DS005501-19

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