ADC10662CIWM datasheet(9/14 Pages) NSC

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Functional Description (Continued)

On the left side of the diagram is a string of seven resistors

connected between V

REF+ and VREF−. Six comparators com-

pare the input voltage with the tap voltages on this resistor

string to provide a low-resolution “estimate” of the input volt-

age. This estimate is then used to control the multiplexer that

connects the MSB Ladder to the sixteen comparators on the

right. Note that the comparators on the left needn’t be very

accurate; they simply provide an estimate of the input volt-

age. Only the sixteen comparators on the right and the six on

the left are necessary to perform the initial six-bit flash con-

version, instead of the 64 comparators that would be re-

quired using conventional half-flash methods.

To perform a conversion, the estimator compares the input

voltage with the tap voltages on the seven resistors on the

left. The estimator decoder then determines which MSB Lad-

der tap points will be connected to the sixteen comparators

on the right. For example, assume that the estimator deter-

mines that V

IN is between 11/16 and 13/16 of VREF. The es-

timator decoder will instruct the comparator MUX to connect

the 16 comparators to the taps on the MSB ladder between

10/16 and 14/16 of V

REF. The 16 comparators will then per-

form the first flash conversion. Note that since the compara-

tors are connected to ladder voltages that extend beyond the

range indicated by the estimator circuit, errors in the estima-

tor as large as 1/16 of the reference voltage (64 LSBs) will

be corrected. This first flash conversion produces the six

most significant bits of data — four bits in the flash itself, and

2 bits in the estimator.

The remaining four LSBs are now determined using the

same sixteen comparators that were used for the first flash

conversion. The MSB Ladder tap voltage just below the input

voltage (as determined by the first flash) is subtracted from

the input voltage and compared with the tap points on the

sixteen LSB Ladder resistors. The result of this second,

four-bit flash conversion is then decoded, and the full 10-bit

result is latched.

Note that the sixteen comparators used in the first flash con-

version are reused for the second flash. Thus, the multistep

conversion technique used in the ADC10662 and ADC10664

needs only a small fraction of the number of comparators

that would be required for a traditional flash converter, and

far fewer than would be used in a conventional half-flash ap-

proach. This allows the ADC10662 and ADC10664 to per-

form high-speed conversions without excessive power drain.

Applications Information

1.0 MODES OF OPERATION

The ADC10662 and ADC10664 have two basic digital inter-

face modes.

Figure 1 and Figure 2 are timing diagrams for

the two modes. The ADC10662 and ADC10664 have input

multiplexers that are controlled by the logic levels on pins S

and S

1 when S /H goes low. Table 1 is a truth table showing

how the input channnels are assigned.

Mode 1

In this mode, the S /H pin controls the start of conversion.

S/H is pulled low for a minimum of 150 ns. This causes the

comparators in the “coarse” flash converter to become ac-

tive. When S /H goes high, the result of the coarse conver-

sion is latched and the “fine” conversion begins. After 360 ns

(typical), INT goes low, indicating that the conversion results

are latched and can be read by pulling RD low. Note that CS

must be low to enable S /H or RD. CS is internally “ANDed”

DS011192-12

FIGURE 3. Block Diagram of the Multistep Converter Architecture

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