ADC12441 datasheet(5/14 Pages) NSC

5 / 14 page

AC Electrical Characteristics (Continued)

Note 4

The power dissipation of this device under normal operation should never exceed 169 mW (Quiescent Power Dissipation a TTL Loads on the digital

outputs) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or

outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction

temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature

is PDmax e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 125 C and the typical thermal

resistance (iJA) of the ADC12441 with CMJ and CIJ suffixes when board mounted is 47 CW

Note 5

Human body model 100 pF discharged through a 15 kX resistor

Note 6

Two on-chip diodes are tied to the analog input as shown below Errors in the AD conversion can occur if these diodes are forward biased more than

50 mV

TLH11017 – 3

This means that if AVCC and DVCC are minimum (475 VDC) and V

is maximum (b475 VDC) full-scale must be s 48 VDC

Note 7

A diode exists between AVCC and DVCC as shown below

TLH11017 – 4

To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin

Note 8

Accuracy is guaranteed at fCLK e 20 MHz At higher and lower clock frequencies accuracy may degrade See curves in the Typical Performance

Characteristics section

Note 9

Typicals are at TJ e 25 C and represent most likely parametric norm

Note 10

Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)

Note 11

Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and

zero For negative linearity error the straight line passes through negative full scale and zero (See

Figures 1b and 1c )

Note 12

The ADC12441’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will

result in a repeatability uncertainty of g020 LSB

Note 13

If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started (see the Typical Performance Characteristic curves)

Note 14

After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes

Note 15

If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of tA therefore making the minimum

tA e 6 clock periods and the maximum tA e 7 clock periods If the falling edge of the clock is synchronous to the rising edge of WR then tA will be exactly 65 clock

periods

Note 16

The CAL line must be high before a conversion is started

Note 17

The specifications for these parameters are valid after an Auto-Cal cycle has been completed

Note 18

The ADC12441 reference ladder is composed solely of capacitors

Note 19

A Military RETS Electrical Test Specification is available on request At time of printing the ADC12441CMJ883 RETS complies fully with the boldface

limits in this column

TLH11017 – 5

FIGURE 1a Transfer Characteristic

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