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MB9DF565MLE Datasheet(PDF) 10 Page - SPANSION |
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MB9DF565MLE Datasheet(HTML) 10 Page - SPANSION |
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10 / 109 page  D at aS he e t May 15, 2015, MB9D560_DS708-00001-3v0-E 9 CONFIDENTIAL Function Description Waveform generator (WFG) − Generate variable output Real time output 16-bit PPG waveform output PPG uses 16-bit PPG timer of base timer The relation is following WFG(ch.0 to ch.5) Base timer ch.0 → PPG0 Base timer ch.2 → PPG2 Base timer ch.4 → PPG4 WFG(ch.6 to ch.11) Base timer ch.6 → PPG6 Base timer ch.8 → PPG8 Base timer ch.10 → PPG10 Non overlap three-phase waveform output (inverter control) DC chopper waveform output − Dead time timer function − GATE function − DTTI function A/D converter (ADC) − 12-bit resolution A/D converter: 1 unit (32 channels) − Sampling analog value from input port of 32 channels − Conversion time: 1 µs − External trigger activation (ADTG) − Activation from internal timer (base timer) 4ch sample-hold A/D converter − 12 bit resolution A/D converter: 2 units (8 channels ) Multi-function serial interface (MFS) − UART / CSIO / LIN interface (v2.1) communication available by selecting the function − Transmission FIFO: 64 Byte, reception FIFO: 64 Byte − Reception interrupt factor (3 types) Reception error detection (parity, over run, frame error) Reception to FIFO for data of setting value Reception data under setting value in FIFO, idle term detection of over 8 clocks with baud rate clock − Transmission interrupt factor (2 types) No transmission operation Transmission FIFO empty (contain transmission operation) − SPI (serial peripheral interface) support − LIN protocol revision 2.1 support Up/Down counter (UDC) − 8/16-bit up/down counter (2 channels uses for R/D converter) CAN interface − The CAN is based on the CAN protocol ver. 2.0A/B − 64 message buffers x 3 channels − An identification mask is applied to each message object − Up to 1Mbps support − Clock support CAN prescaler − CAN wakeup functions FlexRay controller − Supports FlexRay protocol specification v2.1 − Maximum 128 message buffers − 8K Byte message RAM − Variable length of message buffers − Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception FIFO − Host access to the message buffer via input and output buffers − Filtering for slot counter, cycle counter and channels − Maskable interrupts are supported R/D converter (RDC) − Connect to resolver interface D/A converter (DAC) − 10-bit resolution |
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