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AD9262EBZ Datasheet(PDF) 30 Page - Analog Devices |
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AD9262EBZ Datasheet(HTML) 30 Page - Analog Devices |
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30 / 32 page  AD9262 Rev. A | Page 30 of 32 MEMORY MAP Table 25. Memory Map Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Port Config 0x00 0 LSBFIRST SOFTRESET 1 1 SOFTRESET LSBFIRST 0 Chip ID 0x01 CHIPID[7:0] Chip Grade 0x02 1 CHILDID[2:0] Channel Index 0x05 Channel[1:0] Power Modes 0x08 PWRDWN[1:0] PLLENABLE 0x09 PLLENABLE PLL 0x0A PLLLOCKED PLLAUTO PLLMULT[5:0] Analog Input 0x0F BW[1:0] Output Modes 0x14 DRVSTD Interleave OUTENB OUTINV Format[1:0] Output Adjust 0x15 DRVSTR33[1:0] DRVSTR18[1:0] Output Clock 0x16 DCOINV Reference 0x18 EXTREF Output Data 0x101 QEC KOUT[5:0] Overrange 0x111 AUTORST OR_IND ORTHRESH[5:0] QEC1 0x112 DCFRZ PHASEFRZ GAINFRZ DCENB PHASEENB GAINENB QEC2 0x113 DCFRC PHASEFRC GAINFRC MEMORY MAP DEFINITIONS Table 26. Memory Map Definitions Register Address Bit(s) Mnemonic Default Description SPI Port Config 0x00 6, 1 LSBFIRST 0 0: serial interface uses MSB first format 1: serial interface uses LSB first format 5, 2 SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A Chip ID 0x01 [7:0] CHIPID 0x22 0x22: AD9262 Chip Grade 0x02 [5:4] CHILDID 0 0x00: 10 MHz bandwidth 0x10: 5 MHz bandwidth 0x20: 2.5 MHz bandwidth Channel Index 0x05 [1:0] Channel 0 0: both channels addressed simultaneously 1: Channel A only addressed 2: Channel B only addressed 3: both channels addressed simultaneously Power Modes 0x08 [1:0] PWRDWN 0 0x0: normal operation 0x1: power-down (local) 0x2: standby (everything except reference circuits) 0x3: sleep PLLENABLE 0x09 2 PLLENABLE 0 1: enable PLL PLL 0x0A 7 PLLLOCKED 0 0: PLL is not locked 1: PLL is locked 6 PLLAUTO 0 1: PLL autoband enabled [5:0] PLLMULT 0 See Table 10 Analog Input 0x0F [6:5] BW 0 See Table 13 |
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