P82B96 datasheet(5/16 Pages) PHILIPS

5 / 16 page

Philips Semiconductors

Product data

P82B96

Dual bi-directional bus buffer

2004 Mar 26

UNIT

MAX.

TYP.

MIN.

CONDITIONS

PARAMETER

SYMBOL

Input logic switching threshold voltages

VSx, VSy

Input logic voltage LOW (Note 3)

On normal I2C-bus

—

640

600

VSx, VSy

Input logic level HIGH threshold (Note 3)

On normal I2C-bus

700

650

—

dVSx/dT,

dVSy/dT

Temperature coefficient of input thresholds

—

–2

—

mV/K

VRx, VRy

Input logic HIGH level

Fraction of applied VCC

0.58

—

VRx, VRy

Input threshold

Fraction of applied VCC

—

0.5

—

VRx, VRy

Input logic LOW level

Fraction of applied VCC

—

0.42

Logic level threshold difference

VSx, VSy

Input/Output logic level difference (Note 1)

VSX output LOW at 0.2 mA –

VSX input HIGH max

—

NOTES:

1. The minimum value requirement for pull-up current, 200

µA, guarantees that the minimum value for VSX output LOW will always exceed the

minimum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While

the tolerances on absolute levels allow a small probability the LOW from one SX output is recognized by an SX input of another P82B96 this

has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system

would be very susceptible to induced noise and would not support all I2C operating modes.

2. The output logic LOW depends on the sink current. For scaling, see

Application Note AN255.

3. The input logic threshold is independent of the supply voltage.

CHARACTERISTICS

At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Bus Release on VCC Failure

VSx, VSy,

VTx, VTy

VCC voltage at which all buses are

guaranteed to be released

—

dV/dT

Temperature coefficient of guaranteed release

voltage

—

–4

—

mV/K

Buffer response time

Tfall delay

VSx to VTx

VSy to VTy

Buffer time delay on FALLING input between

VSx = input switching threshold,

and VTx output falling 50%.

RTx pull-up = 160 Ω,

no capacitive load, VCC = 5 V

—

Trise delay

VSx to VTx

VSy to VTy

Buffer time delay on RISING input between

VSx = input switching threshold,

and VTx output reaching 50% VCC

RTx pull-up = 160 Ω,

no capacitive load, VCC = 5 V

—

Tfall delay

VRx to VSx

VRy to VSy

Buffer time delay on FALLING input between

VRx = input switching threshold,

and VSx output falling 50%.

RSx pull-up = 1500 Ω, no

capacitive load, VCC = 5 V

—

250

—

Trise delay

VRx to VSx

VRy to VSy

Buffer time delay on RISING input between

VRx = input switching threshold,

and VSx output reaching 50% VCC

RSx pull-up = 1500 Ω,

no capacitive load, VCC = 5 V

—

270

—

Input capacitance

Cin

Effective input capacitance of any signal pin

measured by incremental bus rise times

—

NOTES ON RESPONSE TIME

The fall-time of VTX from 5 V to 2.5 V in the test is approximately 15 ns.

The fall-time of VSX from 5 V to 2.5 V in the test is approximately 50 ns.

The rise-time of VTX from 0 V to 2.5 V in the test is approximately 20 ns.

The rise-time of VSX from 0.9 V to 2.5 V in the test is approximately 70 ns.

P82B96 Datasheet(PDF) 5 Page - NXP Semiconductors

P82B96 Datasheet(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL