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39SF020 Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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39SF020 Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
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9 / 23 page ![]() 9 © 1998 Silicon Storage Technology, Inc. 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VCC = 4.5-5.5V SST39SF020-70 SST39SF020-90 Symbol Parameter Min Max Min Max Units TRC Read Cycle time 70 90 ns TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns TCLZ(1) CE# Low to Active Output 0 0 ns TOLZ(1) OE# Low to Active Output 0 0 ns TCHZ(1) CE# High to High-Z Output 15 20 ns TOHZ(1) OE# High to High-Z Output 15 20 ns TOH(1) Output Hold from Address Change 0 0 ns 326 PGM T9.2 TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte Program time 30 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 0 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH (1) WE# Pulse Width High 30 ns TCPH (1) CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH (1) Data Hold Time 0 ns TIDA (1) Software ID Access and Exit Time 150 ns TSE Sector Erase 10 ms TSCE Chip Erase 20 ms Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 326 PGM T10.4 Note: CL = 100 pF for 90 ns, CL = 30 pF for 70 ns |
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