CY7C1021
Document #: 38-05054 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
1021-3
1021-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 3 ns
< 3 ns
OUTPUT
R 481
Ω
R 481
Ω
R2
255
Ω
R2
255
Ω
167
Equivalent to: THÉVENIN
EQUIVALENT
1.73V
30 pF
Switching Characteristics[5] Over the Operating Range
Parameter
Description
7C1021-10
7C1021-12
7C1021-15
7C1021-20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
10
12
15
20
ns
tAA
Address to Data Valid
10
12
15
20
ns
tOHA
Data Hold from Address Change
3
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
5
6
7
9
ns
tLZOE
OE LOW to Low Z[6]
0
0
0
0
ns
tHZOE
OE HIGH to High Z[6, 7]
5
6
7
9
ns
tLZCE
CE LOW to Low Z[6]
3
3
3
3
ns
tHZCE
CE HIGH to High Z[6, 7]
5
6
7
9
ns
tPU
CE LOW to Power-Up
0
0
0
0
ns
tPD
CE HIGH to Power-Down
10
12
15
20
ns
tDBE
Byte Enable to Data Valid
5
6
7
9
ns
tLZBE
Byte Enable to Low Z
0
0
0
0
ns
tHZBE
Byte Disable to High Z
5
6
7
9
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
12
ns
tAW
Address Set-Up to Write End
7
8
10
12
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
12
ns
tSD
Data Set-Up to Write End
5
6
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
3
3
3
ns
tHZWE
WE LOW to High Z[6, 7]
5
6
7
9
ns
tBW
Byte Enable to End of Write
7
8
9
12
ns
Shaded areas contain preliminary information.
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7.
tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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