Fig. 2 illustrates the differential mode of the CLC431's

disable feature for ECL-type logic. In order for this mode

from Q2 to Q1 and results in the

disabling of that CLC431

channel. Alternatively, applying a differential logic "low"

differential pair from Q1 to Q2 and results in the

enabling

of that same channel. The internal clamp, mentioned

above, also protects against excessive differential volt-

ages up to 30Volts while limiting input currents to <3mA.

DC Performance

A current-feedback amplifier’s input stage does not have

equal nor correlated bias currents, therefore they cannot

be cancelled and each contributes to the total DC offset

voltage at the output by the following equation:

from the non-inverting input back towards the source. For

inverting DC-offset calculations, the source resistance

output offset calculation as a part of the non-inverting

gain equation. Application note OA-7 gives several circuits

for DC offset correction.

Layout Considerations

It is recommended that the decoupling capacitors (0.1

µF

ceramic and 6.8

µF electrolytic) should be placed as close

as possible to the power supply pins to insure a proper

high-frequency low impedance bypass. Careful attention

to circuit board layout is also necessary for best

performance. Of particular importance is the control of

parasitic capacitances (to ground) at the output and

invering input pins. See CLC431/432 Evaluation Board

literature for more information.

Applications Circuits

2:1 Video Mux (CLC431)

Fig. 3 illustrates the connections necessary to configure

the CLC431 as a 2:1 multiplexer in a 75

Ω system. Each

of the two CLC431's amplifiers is configured with a non-

inverting gain of +2V/V using 634

Ω feedback (R

lower than that recommended in order to compensate for

the reduction of loop-gain that results from the inclusion

of the 50

Ω resistor (R

Ω

resistor serves to isolate the output of the active channel

from the impedance of the inactive channel yet does not

affect the low output impedance of the active channel.

with the disable feature are to be connected as follows:

well as

selected with the application of a logic "low" to SELECT

while a logic "high" selects Channel 2.

front page). Also note that both amplifiers are guaranteed

to be enabled if all three of these pins are unconnected.

Fig. 1 illustrates the single-ended mode of the CLC431's

disable feature for logic families such as TTL and CMOS.

two internal series diodes. For single-ended operation,

DIS

should be left floating. Applying a TTL or CMOS logic

"high" (i.e. >2.0Volts) to DIS will switch the tail current of

the differential pair to Q1 and "shut down" Q2 which

results in the

disabling of that channel of the CLC431.

Alternatively, applying a logic "low" (i.e. <0.8Volts) to DIS

will switch the tail current from Q1 to Q2 effectively

enabling that channel. If DIS is left floating under single-

ended operation, then the associated amplifier is guaran-

teed to be

disabled.

The disable feature of the CLC431 is such that DIS and

DIS

temperature range. Internal clamps (not shown) protect

the DIS input from excessive input voltages that could

otherwise cause damage to the device. This condition

occurs when enough source current flows into the node

DIS

DIS

½CLC431

100k

Ω

100k

Ω

TTL

CMOS

+

-

Fig. 1

VI

R

R

R

V

R

R

IR

offset

bn

s

f

g

io

f

g

bi

f

=±

∗

+











 ++











 +∗

















11

5

http://www.national.com

DIS

DIS

100k

Ω

100k

Ω

ECL

510

Ω

-5V

-5V

510

Ω

½CLC431

+

-

Fig. 2