CLC446AMC datasheet(6/12 Pages) NSC

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where

DC Design (DC offsets)

The DC offset model shown in Figure 6 is used to

calculate the output offset voltage. The equation for out-

put offset voltage is:

The current offset terms, IBN and IBI , do not track each

other. The specifications are stated in terms of magni-

tude only. Therefore, the terms Vos, IBN, and IBI can have

either polarity. Matching the equivalent resistance seen

at both input pins does not reduce the output

offset voltage.

Figure 6: DC Offset Model

DC Design (output loading)

RL, Rf, and Rg load the op amp output. The equivalent

load seen by the output in Figure 6 is:

RL(eq) = RL || (Rf + Req2), non-inverting gain

RL(eq) = RL || Rf, inverting gain

RL(eq) needs to be large enough so that the minimum out-

put current can produce the required output voltage

swing.

AC Design (small signal bandwidth)

The CLC446 current-feedback amplifier bandwidth is

a function of the feedback resistor (Rf), not of the DC

voltage gain (AV). The bandwidth is approximately

proportional to

. As a rule, if Rf doubles, the band-

width is cut in half. Other AC specifications will also be

degraded. Decreasing Rf from the recommended value

increases peaking, and

for very small values of Rf oscil-

lation will occur.

AC Design (minimum slew rate)

Slew rate influences the bandwidth of large signal

sinusoids. To determine an approximate value of slew

rate necessary to support a large sinusoid, use the

following equation:

≅ 5 • f • V

peak

where Vpeak is the peak output sinusoidal voltage.

The slew rate of the CLC446 in inverting gains is always

higher than in non-inverting gains.

AC Design (linear phase/constant group delay)

The recommended value of Rf produces minimal

peaking and a reasonably linear phase response.

To improve phase linearity when |Av| < 5, increase Rf

approximately 50% over its recommended value. Some

adjustment of Rf may be needed to achieve phase lin-

earity for your application. See the

AC Design (small

signal bandwidth) sub-section for other effects of

changing Rf.

Propagation delay is approximately equal to group delay.

Group delay is related to phase by this equation:

where

φ(f) is the phase in degrees. Linear phase implies

constant group delay. The technique for achieving linear

phase also produces a constant group delay.

AC Design (peaking)

Peaking is sometimes observed with the recommended

Rf. If a small increase in Rf does not solve the problem,

then investigate the possible causes and remedies

listed below.

Capacitance across Rf

Do not place a capacitor across Rf

Use a resistor with low parasitic

capacitance for Rf

A capacitive load

Use a series resistor between the output and

a capacitive load (see the

Recommended

Rs vs. CL plot)

Long traces and/or lead lengths between Rf and

the CLC446

Keep these traces as short as possible

For non-inverting and transimpedance gain configurations:

Extra capacitance between the inverting pin

and ground (Cg)

See the

Printed Circuit Board Layout sub-

section below for suggestions on reducing Cg

Increase Rf if peaking is still observed after

reducing Cg

For inverting gain configurations:

Inadequate ground plane at the non-inverting pin

and/or long traces between non-inverting pin

and ground

Place a 50 to 200

Ω resistor between the non-

inverting pin and ground (see Rt in Figure 2)

Capacitive Loads

Capacitive loads, such as found in A/D converters,

require a series resistor (Rs) in the output to

improve settling performance.

The

Recommended

Rs vs. CL plot in the Typical Performance

Characteristics section provides the information for

selecting this resistor.

()⋅

=⋅

oos

eq1

eq2

=−

⋅

()⋅+











 +⋅

()

Req1

Req2

CLC446

IBI

IBN

Vos

φφ

360

() =−

⋅

()

≈−

()

∆

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