FM25V02A datasheet(13/23 Pages) CYPRESS

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FM25V02A

Document Number: 001-90865 Rev. *F

Page 13 of 23

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage temperature ............................... –55

C to + 125 C

Maximum accumulated storage time

At 125 °C ambient temperature ................................. 1000 h

At 85 °C ambient temperature ................................ 10 Years

Ambient temperature

with power applied ................................... –55 °C to +125 °C

Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V

Input voltage ........... –1.0 V to +4.5 V and VIN < VDD + 1.0 V

DC voltage applied to outputs

in HI-Z state ........................................ –0.5 V to VDD + 0.5 V

Transient voltage (< 20 ns) on

any pin to ground potential ................. –2.0 V to VDD + 2.0 V

Package power dissipation

capability (TA = 25 °C) ................................................. 1.0 W

Surface mount lead soldering

temperature (3 seconds) ........................................ + 260

C

DC output current (1 output at a time, 1s duration) .... 15 mA

Electrostatic discharge voltage

Human Body Model (JEDEC Std JESD22-A114-B) ................ 2 kV

Charged Device Model (JEDEC Std JESD22-C101-A)........... 500 V

Latch-up current .................................................... > 140 mA

Operating Range

Range

Ambient Temperature

(TA)

VDD

Industrial

–40

C to +85 C

2.0 V to 3.6 V

DC Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min

Typ[3]

Max

Unit

VDD

Power supply

2.0

3.3

3.6

IDD

VDD supply current

SCK toggling between VDD –

0.2 V and VSS, other inputs VSS

or VDD – 0.2 V. SO = Open.

fSCK = 40 MHz

–

2.5

fSCK = 1 MHz

–

0.22

ISB

VDD standby current

CS = VDD. All other inputs VSS or VDD.

–

150

A

IZZ

Sleep mode current

CS = VDD. All other inputs VSS or VDD.–

A

ILI

Input leakage current

(Except HOLD)

VSS < VIN < VDD

–1

–

A

Input leakage current

(for HOLD)

–100

–

A

ILO

Output leakage current

VSS < VOUT < VDD

–1

–

A

VIH

Input HIGH voltage

0.7 × VDD

–VDD + 0.3

VIL

Input LOW voltage

– 0.3

–

0.3 × VDD

VOH1

Output HIGH voltage

IOH = –1 mA, VDD = 2.7 V.

2.4

–

VOH2

Output HIGH voltage

IOH = –100 AVDD – 0.2

–

VOL1

Output LOW voltage

IOL = 2 mA, VDD = 2.7 V

–

0.4

VOL2

Output LOW voltage

IOL = 150 A–

–

0.2

Rin

[4]

Input resistance (HOLD)For VIN = VIL (max)

800

–



For VIN = VIH (min)

–



Notes

3. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.

4. The input pull-up circuit is strong (30 k

) when the input voltage is above V

IH and weak (800 k) when the input voltage is below VIL.

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