CLC5523IM datasheet(10/12 Pages) NSC

10 / 12 page

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Digital Gain Control

Digitally variable gain control can be easily realized

by driving the CLC5523’s gain control input with a

digital-to-analog converter (DAC). Figure 10 illustrates

such an application. This circuit employs National

Semiconductor’s eight-bit DAC0830, the LM351 JFET

input op-amp, and the CLC5523 VGA. With Vref set to 2V,

the circuit provides up to 80dB of gain control in

512 steps with up to 0.05% full scale resolution. The

maximum gain of this circuit is 20dB.

Figure 10: Digital Gain Control

Automatic Gain Control (AGC) #1

Fast Response AGC Loop

The AGC circuit shown in Figure 11 will correct a 6dB

input amplitude step in 100ns. The circuit includes a two

op-amp precision rectifier amplitude detector (U1 and

U2), and an integrator (U3) to provide high loop gain at

low frequencies. The output amplitude is set by R9.

Some notes on building fast AGC loops:

Precision rectifiers work best with large output signals.

Accuracy is improved by blocking DC offsets, as shown in

Figure 11.

Signal frequencies must not reach the gain control port of

the CLC5523, or the output signal will be distorted

(modulated by itself).

A fast settling AGC needs

additional filtering beyond the integrator stage to

block signal frequencies. This is provided in Figure 11

by a simple R-C filter (R10 and C3); better distortion

performance can be achieved with a more complex filter.

These filters should be scaled with the input signal

frequency.

Loops with slower response time (longer

integration time constants) may not need the R10 –

C3 filter.

Checking the loop stability can be done by monitoring the

Vg voltage while applying a step change in input signal

amplitude. Changing the input signal amplitude can be

easily done with either an arbitrary waveform generator

or a fast multiplexer such as the CLC532.

Automatic Gain Control (AGC) #2

Figure 12 on the following page, illustrates an automatic

gain control circuit that employs two CLC5523’s. In this

circuit, U1 receives the input signal and produces an

output signal of constant amplitude. U2 is configured

to provide negative feedback. U2 generates a rectified

gain control signal that works against an adjustable

bias level which may be set by the potentiometer and

Rb.Ci integrates the bias and negative feedback. The

resultant gain control signal is applied to the U1 gain

control input Vg. The bias adjustment allows the U1

output to be set at an arbitrary level less than the

maximum

output

specification

the

amplifier.

Rectification is accomplished in U2 by driving both

the amplifier input and the gain control input with the

U1 output signal. The voltage divider that is formed

by R1, R2 and the Vg input (pin 1) resistance, sets the

rectifier gain.

CLC5523 Applications

CLC5523

100

Vin

LM351

DAC0830

Io2

Io1

Rfb

Vref

Digital

Input

CLC5523

Output

20MHz,

0.1Vpp

Vin

100

CLC426

R10

500

40pF

680pF

4.22k

-5V

500

CLC404

500

CLC404

1N5712

Schottky

500

1.0

Includes scope

probe capacitance

Figure 11: Automatic Gain Control Circuit #1

CLC5523IM Datasheet(PDF) 10 Page - National Semiconductor (TI)

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