CLC5632 datasheet(14/19 Pages) NSC

14 / 19 page

Application Division (Continued)

Load Termination

The CLC5632 can source and sink near equal amounts of

current. For optimum performance, the load should be tied to

CM.

Driving Cables and Capacitive Loads

When driving cables, double termination is used to prevent

reflections. For capacitive load applications, a small series

resistor at the output of the CLC5632 will improve stability

and settling performance. The Frequency Response vs. C

plot, shown below in

Figure 10, gives the recommended

series resistance value for optimum flatness at various ca-

pacitive loads.

Transmission Line Matching

One method for matching the characteristic impedance (Z

of a transmission line or cable is to place the appropriate

resistor at the input or output of the amplifier.

Figure 11

shows typical inverting and non-inverting circuit configura-

tions for matching transmission lines.

Non-Inverting gain applications:

•

Connect pin 2 as indicated in the table in the Closed

Loop Gain Selection section.

•

Make R

1,R2,R6, and R7 equal to ZO.

•

Use R

3 to isolate the amplifier from reactive loading

caused by the transmission line, or by parasitics.

Inverting gain applications:

•

Connect R

3 directly to ground.

•

Make the resistors R

4,R6, and R7 equal to ZO.

•

Make R

5 \ Rg =ZO.

The input and output matching resistors attenuate the signal

by a factor of 2, therefore additional gain is needed. Use C6

to match the output transmission line over a greater fre-

quency range. C6 compensates for the increase of the am-

plifier’s output impedance with frequency.

Power Dissipation

Follow these steps to determine the power consumption of

the CLC5632:

1. Calculate the quiescent (no-load) power: P

amp

CC−VEE)

2. Calculate the RMS power at the output stage: P

O =(VCC

−V

load)(Iload), where Vload and Iload are the RMS voltage and

current across the external load.

3. Calculate the total RMS power: P

t =Pamp+PO The maxi-

mum power that the DIP and SOIC, packages can dissipate

at a given temperature is illustrated in

Figure 12. The power

derating curve for any CLC5632 package can be derived by

utilizing the following equation:

where

amb = Ambient temperature (˚C)

JA = Thermal resistance, from junction to ambient, for a

given package (˚C/W)

Layout Considerations

A proper printed circuit layout is essential for achieving high

frequency performance. National provides evaluation boards

for the CLC5632 (CLC730038-DIP, CLC730036-SOIC) and

suggests their use as a guide for high frequency layout and

as an aid for device testing and characterization.

General layout and supply bypassing play major roles in high

frequency performance. Follow the steps below as a basis

for high frequency layout:

•

Include 6.8µF tantalum and 0.1µF ceramic capacitors on

both supplies.

•

Place the 6.8µF capacitors within 0.75 inches of the

power pins.

•

Place the 0.1µF capacitors less than 0.1 inches from the

power pins.

DS015003-48

FIGURE 10. Frequency Response vs. C

Ω

CLC5632

V2 +-

Note: Channel 2 not shown.

DS015003-49

FIGURE 11. Transmission Line Matching

DS015003-51

FIGURE 12. Power Derating Curve

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