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TP3465 Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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TP3465 Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 17 page  Functional Description (Continued) TABLE I Control and Data Registers Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00h SMB d7 d6 d5 d4 d3 d2 d1 d0 01h FMB d7 d6 d5 d4 d3 d2 d1 d0 02h FMBD0 d7 d6 d5 d4 d3 d2 d1 d0 03h FMBD1 d7 d6 d5 d4 d3 d2 d1 d0 04h FMBD2 d7 d6 d5 d4 d3 d2 d1 d0 05h FMBD3 d7 d6 d5 d4 d3 d2 d1 d0 06h FMBD4 d7 d6 d5 d4 d3 d2 d1 d0 07h FMBD5 d7 d6 d5 d4 d3 d2 d1 d0 08h FMBD6 d7 d6 d5 d4 d3 d2 d1 d0 09h FMBD7 d7 d6 d5 d4 d3 d2 d1 d0 0Ah CS cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 0Bh SKP skp7 skp6 skp5 skp4 skp3 skp2 skp1 skp0 0Ch MWM mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0 0Dh SKR inten soi ms 0 0 div2 div1 div0 0Eh ST uwdone 0 0 0 0 0 0 0 0Fh PD pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 PDPin Definition Register W Register RESET condition is FFhex (all pins as Inputs) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd0–7 bits configure the CS0 – 7 pins as inputs or outputs For example pd0 e 1 sets the CS0 pin as an input pd0 e 0 sets CS0 pin as an output Upon chip RESET the pd0–7 bits are set to 1 SKPMICROWIRE Clock (SK) Polarity W Register RESET condition is 00hex (Normal MICROWIRE clock) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 skp7 skp6 skp5 skp4 skp3 skp2 skp1 skp0 skp 0 – 7 bits set the polarity of the SK MICROWIRE clock when communicating with device connected to each of the pins CS0 – 7 For example skp0 e 0 normal MICROWIRE mode (ie SO data output on negative edge of SK clock) when sending data to device controlled by CS0 pin skp1 e 1 NSC COMBO II clock format for device controlled by CS1 (ie SO data output on the positive edge of SK clock) MWMMICROWIRE Mode Register W Register RESET condition is 00hex Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0 mwm0 – 7 bits specify whether 8 or 16 clocks are generated for devices connected to CS0 – 7 pins For example mwm1 e 1 16 clocks will be generated for device controlled by CS1 (16 data bits will be shifted out and 16 data bits will be strobed in) mwm0 e 0 8 clocks will be generated for de- vice controlled by CS0 (8 data bits will be shifted out and strobed in) SKRMICROWIRE Clock (SK) Rate Register W Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 inten soi ms 0 0 div2 div1 div0 The 3 bits div0 – 2 give the divide-by value for deriving the SK clock output rate from the CKIN The maximum CKIN rate is 20 MHz and the slowest MICROWIRE peripheral works at 256 kHz Table 2 below gives the division ratios and some examples div2 div1 div0 SK Ratio eg CKIN e 5 MHz eg CKIN e 20 MHz 000 SK e CKIN SK e 5 MHz 001 SK e CKIN2 SK e 25 MHz 010 SK e CKIN4 e 125 MHz SK e 5 MHz 011 SK e CKIN8 e 625 kHz e 25 MHz 100 SK e CKIN16 e 3125 kHz e 125 MHz 101 SK e CKIN32 e 15625 kHz e 625 kHz 110 SK e CKIN64 e 78125 kHz e 3125 kHz 111 SK e CKIN128 e 3906 kHz e 15625 kHz TABLE 2 SK Clock Rate Control 5 |
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