COP884BC datasheet(21/57 Pages) NSC

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Multi-Input Wake Up (Continued)

CAN RECEIVE WAKE UP

The CAN Receive Wake Up source is always enabled and is

always active on a falling edge of the CAN comparator out-

put. There is no specific enable bit for the CAN Wake Up fea-

ture. Although the wake up feature on pins L0..L6 can be

programmed to generate an interrupt (L-port interrupt), no in-

terrupt is generated upon a CAN receive wake up condition.

The CAN block has its own, dedicated receiver interrupt

upon receive buffer full.

PORT L INTERRUPTS

Port L provides the user with an additional seven fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The GIE (global interrupt enable) bit enables the interrupt

function. A control flag, LPEN, functions as a global interrupt

enable for Port L interrupts. Setting the LPEN flag will enable

interrupts and vice versa. A separate global pending flag is

not needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

The Wake Up signal will not start the chip running immedi-

ately since crystal oscillators or ceramic resonators have a fi-

nite start up time. The IDLE Timer (T0) generates a fixed de-

lay to ensure that the oscillator has indeed stabilized before

allowing the device to execute instructions. In this case,

upon detecting a valid Wake Up signal, only the oscillator cir-

cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is

loaded with a value of 256 and is clocked from the t

c instruc-

tion cycle clock. The t

c clock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following

the CKI on-chip inverter ensures that the IDLE timer is

clocked only when the oscillator has a sufficiently large am-

plitude to meet the Schmitt trigger specifications. This

Schmitt trigger is not part of the oscillator closed loop. The

start-up time-out from the IDLE timer enables the clock sig-

nals to be routed to the rest of the chip.

CAN Block Description *

This device contains a CAN serial bus interface as described

in the CAN Specification Rev. 2.0 part B.

*Patents Pending.

CAN Interface Block

This device supports applications which require a low speed

CAN interface. It is designed to be programmed with two

transmit and two receive registers. The user’s program may

check the status bytes in order to get information of the bus

state and the received or transmitted messages. The device

has the capability to generate an interrupt as soon as one

byte has been transmitted or received. Care must be taken if

more than two bytes in a message frame are to be

transmitted/received. In this case the user’s program must

poll the transmit buffer empty (TBE)/receive buffer full (RBF)

bits or enable their respective interrupts and perform a data

exchange between the user data and the Tx/Rx registers.

DS012067-16

FIGURE 16. Multi-Input Wake Up Logic

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