COP684BC datasheet(19/57 Pages) NSC

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Timers (Continued)

comes greater than RLON, the PWPND bit in the PWM con-

trol register is set to “1”. If the PWIE bit is also set to “1”, the

PWPND bit is enabled to request an interrupt.

It should be noted that two other conditions could also set

the PWPND bit:

If the mode of operation is changed on the fly the timer

output will toggle. If frequency monitor mode is entered

on the fly such that the timer output changes from 0 to 1,

PWPND will be set.

If the timer is operating in frequency monitor mode and

the RLON value is changed on the fly so that RLON be-

comes less than the current timer value, PWPND will be

set.

The PWPND bit remains set until the user’s software writes

a “0” to it. If the software writes a “1” to the PWPND bit, this

has no effect. If the software writes a “0” to the PWPND bit at

the same time as the hardware writes to the bit, the hard-

ware has precedence. (See

Figure 17 for Frequency Monitor

Mode Operation.)

Note: If the clock to the device stops while PWM0 is high,

and a subsequent Reset occurs while the clock is stopped,

the PWM0/L6 output will be put in the weak pull-up mode un-

til the clock resumes.

Power Save Modes

The device offers the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry and timer T0 are active but all other microcon-

troller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

HALT MODE

The contents of all PWM Timer registers are frozen during

HALT mode and are left unchanged when exiting HALT

mode. The PWM timer resumes its previous mode of opera-

tion when exiting HALT mode.

The device is placed in the HALT mode by writing a “1” to the

HALT flag (G7 data bit). All microcontroller activities, includ-

ing the clock, and timers, are stopped. In the HALT mode,

the power requirements of the device are minimal and the

applied voltage (V

CC) may be decreased to Vr (Vr = 2.0V)

without altering the state of the machine.

The device supports two different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wake Up feature on the L port. The second

method of exiting the HALT mode is by pulling the RESET

pin low.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wake Up signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wake Up signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the t

c instruction cycle clock. The tc

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The start-up time-out from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a “1” to the HALT flag will have no ef-

fect).

IDLE MODE

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activities, except the

associated on-board oscillator circuitry, and the IDLE Timer

DS012067-15

FIGURE 15. Frequency Monitor Mode Operation

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