LT1715IMS datasheet(13/16 Pages) LINER

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LT1715

The level translator designs assume one gate load. Mul-

tiple gates can have significant IIH loading, and the trans-

mission line routing and termination issues also make this

case difficult.

ECL, and particularly PECL, is valuable technology for

high speed system design, but it must be used with care.

With less than a volt of swing, the noise margins need to

be evaluated carefully. Note that there is some degrada-

tion of noise margin due to the

±5% resistor selections

shown. With 10KH/E, there is no temperature compensa-

tion of the logic levels, whereas the LT1715 and the

circuits shown give levels that are stable with tempera-

ture. This will lower the noise margin over temperature.

In some configurations it is possible to add compensation

with diode or transistor junctions in series with the

resistors of these networks.

For more information on ECL design, refer to the ECLiPS

data book (DL140), the 10KH system design handbook

(HB205) and PECL design (AN1406), all from Motorola,

now ON Semiconductor.

Circuit Description

The block diagram of the LT1715 is shown in Figure 9. The

circuit topology consists of a differential input stage, a

gain stage with hysteresis and a complementary com-

mon-emitter output stage. All of the internal signal paths

utilize low voltage swings for high speed at low power.

The input stage topology maximizes the input dynamic

range available without requiring the power, complexity

and die area of two complete input stages such as are

found in rail-to-rail input comparators. With a single 2.7V

supply, the LT1715 still has a respectable 1.6V of input

common mode range. The differential input voltage range

is rail-to-rail, without the large input currents found in

competing devices. The input stage also features phase

reversal protection to prevent false outputs when the

inputs are driven below the –100mV common mode

voltage limit.

The internal hysteresis is implemented by positive, nonlin-

ear feedback around a second gain stage. Until this point,

the signal path has been entirely differential. The signal

path is then split into two drive signals for the upper and

lower output transistors. The output transistors are con-

nected common emitter for rail-to-rail output operation.

The Schottky clamps limit the output voltages at about

300mV from the rail, not quite the 50mV or 15mV of Linear

Technology’s rail-to-rail ampliﬁers and other products.

But the output of a comparator is digital, and this output

stage can drive TTL or CMOS directly. It can also drive ECL,

as described earlier, or analog loads.

The bias conditions and signal swings in the output stage

are designed to turn their respective output transistors off

faster than on. This helps minimize the surge of current

from + VS to ground that occurs at transitions, to minimize

APPLICATIO S I FOR ATIO

Figure 9. LT1715 Block Diagram

–

+IN

–IN

AV1

VCC

VEE

AV2

NONLINEAR STAGE

OUT

GND

1715 F09

+VS

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