COP8CDR9 datasheet(38/84 Pages) NSC

38 / 84 page

12.0 Timers (Continued)

12.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in Mode

3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (TxC3, TxC2 and TxC1) are

detailed in Table 15, Timer Operating Modes.

When the high speed timers are counting in high speed

mode, directly altering the contents of the timer upper or

lower registers, the PWM outputs or the reload registers is

not recommended. Bit operations can be particularly prob-

lematic. Since any of these six registers or the PWM outputs

can change as many as ten times in a single instruction

cycle, performing an SBIT or RBIT operation with the timer

running can produce unpredictable results. The recom-

mended procedure is to stop the timer, perform any changes

to the timer, the PWM outputs or reload register values, and

then re-start the timer. This warning does not apply to the

timer control register. Any type of read/write operation, in-

cluding SBIT and RBIT may be performed on this register in

any operating mode.

TABLE 15. Timer Operating Modes

Mode

TxC3

TxC2

TxC1

Description

Interrupt A

Source

Interrupt B

Source

Timer

Counts On

PWM: TxA Toggle

Autoreload RA

Autoreload RB

C or MCLK

PWM: No TxA

Toggle

Autoreload RA

Autoreload RB

C or MCLK

External Event

Counter

Timer Underflow

Pos. TxB Edge

TxA Pos.

Edge

External Event

Counter

Timer Underflow

Pos. TxB Edge

TxA Neg.

Edge

Captures:

Pos. TxA Edge

Pos. TxB Edge

C or MCLK

TxA Pos. Edge

or Timer

TxB Pos. Edge

Underflow

Captures:

Pos. TxA

Neg. TxB

C or MCLK

TxA Pos. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Captures:

Neg. TxA

Pos. TxB

C or MCLK

TxA Neg. Edge

Edge or Timer

Edge

TxB Pos. Edge

Underflow

Captures:

Neg. TxA

Neg. TxB

C or MCLK

TxA Neg. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

13.0 Power Saving Features

Today, the proliferation of battery-operated applications has

placed new demands on designers to drive power consump-

tion down. Battery operated systems are not the only type of

applications demanding low power. The power budget con-

straints are also imposed on those consumer/industrial ap-

plications where well regulated and expensive power supply

costs cannot be tolerated. Such applications rely on low cost

and low power supply voltage derived directly from the

10137421

FIGURE 18. Timer in Input Capture Mode

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