COPCJ823 datasheet(20/35 Pages) NSC

20 / 35 page

Modulator/Timer (Continued)

Comparator

The device has one differential comparator. Ports L0–L2 are

used for the comparator. The output of the comparator is

brought out to a pin. Port L has the following assignments:

L0 Comparator output

L1 Comparator negative input

L2 Comparator positive input

THE COMPARATOR STATUS/CONTROL BITS

These bits reside in the CNTRL2 Register (Address 0CC)

CMPEN Enables comparator (“1” = enable)

CMPRD Reads comparator output internally

(CMPEN = 1, CMPOE=X)

CMPOE Enables comparator output to pin L0

(“1”=enable), CMPEN bit must be set to enable

this function. If CMPEN=0, L0 will be 0.

The Comparator Select/Control bits are cleared on RESET

(the comparator is disabled). To save power the program

should also disable the comparator before the device enters

the HALT mode.

The user program must set up L0, L1 and L2 ports correctly

for comparator Inputs/Output: L1 and L2 need to be config-

ured as inputs and L0 as output. See

Table 9.

TABLE 9. Comparator DC and AC Characteristics

≤ V

CC ≤ 6V, −40˚C ≤ TA ≤ + 85˚C (Note 7)

Parameters

Conditions

Min

Type

Max

Units

Input Offset Voltage

0.4V < V

IN < VCC − 1.5V

±10

±25

Input Common Mode Voltage Range

0.4

CC − 1.5

Voltage Gain

300k

V/V

DC Supply Current (when enabled)

CC = 6.0V

250

µA

Response Time

100 mV Overdrive

100

140

500 mV Overdrive

125

165

1000 mV Overdrive

135

215

300

Note 12: For comparator output current characteristics see L-Port specs.

DS011208-18

FIGURE 14. Mode 2a: 50% Duty Cycle Output

DS011208-19

DS011208-20

FIGURE 15. Mode 2b: Variable Duty Cycle Output

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