OPA656 datasheet(15/20 Pages) TI

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OPA657

SBOS197B

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This would be the worst-case error band in volume produc-

tion at 25

°C acceptance testing given the conditions stated.

Over the temperature range (0

°C to 70°C), we can expect the

following worst-case shifting from initial value. A 20

°C inter-

nal junction self-heating is assumed here.

±0.36mV (OPA656 high-grade input offset drift)

±6µV/°C • (70°C + 20°C – 25°C)

±0.11mV (–PSRR of 66dB with 5mV • (70°C – 25°C) supply shift)

±0.04mV (+PSRR of 76dB with 5mV • (70°C – 25°C) supply shift)

Total =

±0.51mV

This would be the worst-case shift from an initial offset over

a 0

°C to 70°C ambient for the conditions stated. Typical initial

output DC error bands and shifts over temperature will be

much lower than these worst-case estimates.

In the transimpedance configuration, the CMRR errors can

be neglected since the input common-mode voltage is held

at ground. For noninverting gain configurations (Figure 1),

the CMRR term will need to be considered but will typically

be far lower than the input offset voltage term. With a tested

minimum of 91dB (28uV/V), the added apparent DC error will

be no more than

±0.06mV for a ±2V input swing to the circuit

of Figure 1.

POWER-SUPPLY CONSIDERATIONS

The OPA657 is intended for operation on

±5V supplies.

Single-supply operation is allowed with minimal change from

the stated specifications and performance from a single

supply of +8V to +12V maximum. The limit to lower supply

voltage operation is the useable input voltage range for the

JFET-input stage. Operating from a single supply of +12V

can have numerous advantages. With the negative supply at

ground, the DC errors due to the –PSRR term can be

minimized. Typically, AC performance improves slightly at

+12V operation with minimal increase in supply current.

THERMAL ANALYSIS

The OPA657 will not require heatsinking or airflow in most

applications. Maximum desired junction temperature will set

the maximum allowed internal power dissipation as de-

scribed below. In no case should the maximum junction

temperature be allowed to exceed 175

°C.

Operating junction temperature (TJ) is given by TA + PD • θJA.

The total internal power dissipation (PD) is the sum of

quiescent power (PDQ) and additional power dissipated in the

output stage (PDL) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total

supply voltage across the part. PDL will depend on the

required output signal and load but would—for a grounded

resistive load—be at a maximum when the output is fixed at

a voltage equal to 1/2 of either supply voltage (for equal

bipolar supplies). Under this condition PDL = VS2/(4 • RL)

where RL includes feedback network loading.

Note that it is the power in the output stage and not into the

load that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using an

OPA657N (SOT23-5 package) in the circuit of Figure 1

operating at the maximum specified ambient temperature of

+85

°C and driving a grounded 100Ω load.

PD = 10V • 16.1mA + 52 /(4 • (100Ω || 500Ω)) = 236mW

Maximum TJ = +85°C + (0.24W • 150°C/W) = 121°C.

All actual applications will be operating at lower internal

power and junction temperature.

BOARD LAYOUT

Achieving optimum performance with a high-frequency am-

plifier like the OPA657 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Parasitic capacitance on the output and

inverting input pins can cause instability—on the noninverting

input, it can react with the source impedance to cause

unintentional bandlimiting. To reduce unwanted capacitance,

a window around the signal I/O pins should be opened in all

of the ground and power planes around those pins. Other-

wise, ground and power planes should be unbroken else-

where on the board.

b) Minimize the distance (< 0.25”) from the power-supply

pins to high-frequency 0.1uF decoupling capacitors. At the

device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections should always be decoupled with these capaci-

tors. Larger (2.2

µF to 6.8µF) decoupling capacitors, effective

at lower frequency, should also be used on the supply pins.

These may be placed somewhat farther from the device and

may be shared among several devices in the same area of

the PC board.

c) Careful selection and placement of external components

will preserve the high frequency performance of the OPA657.

Resistors should be a very low reactance type. Surface-mount

resistors work best and allow a tighter overall layout. Metal film

and carbon composition axially leaded resistors can also pro-

vide good high-frequency performance. Again, keep their leads

and PC board trace length as short as possible. Never use

wirewound-type resistors in a high-frequency application. Since

the output pin and inverting input pin are the most sensitive to

parasitic capacitance, always position the feedback and series

output resistor, if any, as close as possible to the output pin.

Other network components, such as noninverting input termina-

tion resistors, should also be placed close to the package.

Where double-side component mounting is allowed, place the

feedback resistor directly under the package on the other side

of the board between the output and inverting input pins. Even

with a low parasitic capacitance shunting the external resistors,

excessively high resistor values can create significant time

constants that can degrade performance. Good axial metal film

or surface-mount resistors have approximately 0.2pF in shunt

with the resistor. For resistor values > 1.5k

Ω, this parasitic

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