PC87413 datasheet(100/257 Pages) NSC

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5.0 X-Bus Extension (Continued)

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100

Revision1.2

5.2.8

Mode 1, Normal Address Transactions

Read and write transactions in mode 1 use an Enable signal and a R/W signal controlled protocol. At least two idle cycles

are inserted at the end of each X-Bus transaction cycle (though there may be more idle cycles due to the LPC transactions).

This mode is selected for transactions accessing XCSn by setting TRANSMD = 1 in the corresponding XZMn register.

Read Transactions. When a read cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus

functional block (or an indirect read is started or an X-Bus read through the ACCESS.bus is started) and the relevant XCSn

is set to mode 1, a Mode 1 read cycle begins. A Mode 1 read cycle (see Figure 21) begins with the de-assertion of XRD_XEN

(set low). At the same time, the address is driven on the XA11-0. Ten CLK cycles later, XCSn is asserted (set low). After ﬁve

CLK cycles, XRD_XEN is asserted (set high) and remains asserted for 18 cycles plus the internally programmed wait state

period. During the period that XRD_XEN is asserted, the data must be driven on XD7-0 by the target device. XRD_XEN is

then de-asserted for two CLK cycles. The data from XD7-0 is sampled at the rising edge of the clock one CLK cycle before

XRD_XEN is de-asserted. At the end of these two CLK cycles, XCSn is set high, and after one CLK cycle, XRD_XEN is also

set high. One CLK cycle later, the address lines XA11-0 are driven low.

Figure 21. Mode 1, Normal Address X-Bus Transaction - Read Access Cycle

Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of the X-Bus

functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started) and the relevant XCSn

is set to mode 1, a Mode 1 write cycle begins. A mode 1 write cycle (see Figure 22) begins with a de-assertion of XRD_XEN

(set low). At the same time, the address is driven on the XA11-0 and the data is driven on XD7-0. After ten CLK cycles, XCSn

and XWR_XRW are asserted (set low). After ﬁve CLK cycles, XRD_XEN is asserted (set high) and remains asserted for 18

cycles plus the internally programmed wait state period. XRD_XEN is then de-asserted for two CLK cycles. At the end of

these two CLK cycles, XCSn is set high. After another CLK cycle, XWR_XRW and XRD_XEN are set high. Address lines

XA11-0 are driven low one CLK cycle later (at the end of the transaction).

CLK

(Internal; for Reference Only)

XD7-0

XA11-0

XCSn

XWR_XRW

XRD_XEN

Data In

Insert: 16 + “Programmed Wait States” CLK cycles.

During this time, non-clock signals do not change.

Insert: 8 CLK cycles.

PC87413 Datasheet(PDF) 100 Page - National Semiconductor (TI)