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PC87413 Datasheet(PDF) 140 Page - National Semiconductor (TI) |
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PC87413 Datasheet(HTML) 140 Page - National Semiconductor (TI) |
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140 / 257 page  7.0 General-Purpose Input/Output (GPIO) Ports (Continued) www.national.com 140 Revision1.2 7.4.2 GPIO Port Runtime Register Map All these registers are VSB powered. 7.4.3 GPIO Data Out Register (GPDO) Power Well:VSB Location:Device specific Type: R/W 7.4.4 GPIO Data In Register (GPDI) Power Well:VSB Location:Device specific Type: RO Offset Mnemonic Register Name Type Power Well Reset Section Device specific1 1. The location of this register is defined in Section 3.14.1 on page 70. GPDO GPIO Data Out R/W VSB FFh 7.4.3 Device specific1 GPDI GPIO Data In RO VSB - 7.4.4 Device specific1 GPEVEN GPIO Event Enable R/W VSB 00h 7.4.5 Device specific1 GPEVST GPIO Event Status R/W1C VSB 00h 7.4.6 Bit 76543210 Name DATAOUT Reset 11111111 Bit Description 7-0 DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the specific Port. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value and configuration. 0: Corresponding pin driven to low 1: Corresponding pin driven or released (according to buffer type selection) to high (default) Bit 76543210 Name DATAIN Reset XXXXXXXX Bit Description 7-0 DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the specific Port. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the GPDO register value may influence the pin value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high |
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