2003 Oct 31

13

Philips Semiconductors

Preliminary specification

Controller for power supply

and battery management

PCF50603

8.1.5

Fig.7 is applicable for all debounce filters in the PCF50603.

handbook, full pagewidth

MDB684

tdebounce

falling edge

interrupts

debounced

un-debounced

rising edge

tdebounce

Fig.7 Definition of debounce filter.

The debounced signal keeps the old value until the new value has been stable for at least the applicable debounce time. Any spike (>30 ms) in the

original signal will reset the debounce timer again. This filter suppresses all signal changes that are shorter than the debounce time.

8.2

including applications, is given in the brochure: The

8.3

Interrupt controller (INT)

The PCF50603 uses the interrupt controller to indicate to

the system controller if the status of the PCF50603 change

and that an action of the system controller is required.

Interrupts can be generated by several modules of the

PCF50603. The interrupt generator handles all interrupts

with the same priority. Priority setting shall be done by the

system controller software.

There are no timing requirements for interrupt service

response times. All events that require immediate actions

are performed by the PCF50603 without any action by the

system controller.

The function of the interrupt module is to capture, mask

and combine the interrupt signals from the modules that

can generate an interrupt. All interrupts are combined in

the interrupt signal IRQ_N. The IRQ_N signal is

implemented as an open-drain output with an internal

pull-up resistor.

The interrupt module is powered in all states (except

NOPOWER) and retains the register values. Events that

occur in the STANDBY state, are captured and can be

read out by the system controller once the system is in the

ACTIVE state.

The IRQ_N signal is asserted in the ACTIVE state

whenever one or more PCF50603 interrupts are active.

Each interrupt register (8-bits) is cleared when it is read

occur during a R&C action are captured in an intermediate

register (see Figs.8 and 9).

All interrupts related to shut-down conditions (LOWBAT,

ONKEY1S and HIGHTMP) are automatically cleared on a

transition from ACTIVE to STANDBY state.

All interrupts can be masked: this effectively prevents that

IRQ_N is asserted for masked interrupts. Masking is

implemented with a mask bit in the mask registers for each

interrupt source. Nevertheless, the interrupt status

registers still provide the actual interrupt status of the

masked interrupts, which allows polling of the interrupt

status registers. Note that if the mask bit is cleared for an

active interrupt, the IRQ_N line goes LOW at the next

falling edge of the output pin CLK32K.