DAC1006LCWM datasheet(17/22 Pages) NSC

17 / 22 page

70 MICROPROCESSOR INTERFACE

The logic functions of the DAC1006 family have been ori-

ented towards an ease of interface with all popular mPs The

following sections discuss in detail a few useful interface

schemes

71 DAC100112 to INS8080A Interface

Figure 18 illustrates the simplicity of interfacing the

DAC1006 to an INS8080A based microprocessor system

The circuit will perform an automatic transfer of the 10 bits

of output data from the CPU to the DAC register as outlined

in Section 621 ‘‘Controlling Data Transfer for an 8-Bit Data

Bus’’

Since a double byte write is necessary to control the DAC

with the INS8080A a possible instruction to achieve this is a

PUSH of a register pair onto a ‘‘stack’’ in memory The 16-

bit register pair word will contain the 10 bits of the eventual

DAC input data in the proper sequence to conform to both

TLH5688 – 24

NOTE DOUBLE BYTE STORES CAN BE USED

eg THE INSTRUCTION SHLD F001 STORES THE L

REG INTO B1 AND THE H REG INTO B2 AND

TRANSFERS THE RESULT TO THE DAC REGISTER

THE OPERAND OF THE SHLD INSTRUCTION MUST

BE AN ODD ADDRESS FOR PROPER TRANSFER

FIGURE 18 Interfacing the DAC1000 to the INS8080A CPU Group

DAC1006LCWM Datasheet(PDF) 17 Page - National Semiconductor (TI)