COP8CSDR9KMT7 datasheet(26/80 Pages) NSC

26 / 80 page

10.0 Functional Description

(Continued)

10.9.5 T3CNTRL Register (Address X'00B6)

T3C3

T3C2

T3C1

T3C0

T3PNDA

T3ENA

T3PNDB

T3ENB

Bit 7

Bit 0

The T3CNTRL register contains the following bits:

T3C3

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C1

Timer T3 mode control bit

T3C0

Timer

Start/Stop

control

timer

modes 1 and 2, Timer T3 Underflow Interrupt

Pending Flag in timer mode 3

T3PNDA Timer T3 Interrupt Pending Flag (Autoreload

RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENB

Timer T3 Interrupt Enable for T3B Input capture

edge

10.9.6 HSTCR Register (Address X'00AF)

Reserved

T3HS

T2HS

Bit 7

Bit 0

The HSTCR register contains the following bits:

T3HS Places Timer T3 in High Speed Mode.

T2HS Places Timer T2 in High Speed Mode.

10.9.7 ITMR Register (Address X'00CF)

LSON

HSON

DCEN

CCKS

RSVD

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 0

The ITMR register contains the following bits:

LSON

Turns the low speed oscillator on or off.

HSON

Turns the high speed oscillator on or off.

DCEN

Selects the high speed oscillator or the low

speed oscillator as the Idle Timer Clock.

CCKSEL Selects the high speed oscillator or the low

speed oscillator as the primary CPU clock.

RSVD

This bit is reserved and must be 0.

ITSEL2

Idle Timer period select bit.

ITSEL1

Idle Timer period select bit.

ITSEL0

Idle Timer period select bit.

COP8CSDR9KMT7 Datasheet(PDF) 26 Page - National Semiconductor (TI)

COP8CSDR9KMT7 Datasheet(HTML) 26 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL