EM78P447SB datasheet(23/55 Pages) EMC

23 / 55 page

EM78P447S

OTP ROM

4.6 Interrupt

The EM78P447S has two interrupts listed below:

(1) TCC overflow interrupt

(2) External interrupt (/INT pin).

R3F is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is the interrupt

mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When

one of the interrupts (enabled) occurs, the next instruction will be fetched from address 001H. Once in the interrupt

service routine, the source of an interrupt can be determined by polling the flag bits in R3F. The interrupt flag bit

must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to

avoid recursive interrupts.

The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the

execution of ENI. Note that the outcome of R3F are the logic AND of R3F and IOCF (refer to Fig. 9). The RETI

instruction ends the interrupt routine and enables the global interrupt (the execution of ENI).

When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from address

002H.

INT

ENI/DISI

IOD

RFWR

IOCFRD

IOCFWR

IRQn

IRQm

RFRD

IOCF

/RESET

/IRQn

VCC

CLK

Fig. 9 Interrupt Input Circuit

This specification is subject to change without prior notice.

06.25.2003 (V1.1)

EM78P447SB Datasheet(PDF) 23 Page - ELAN Microelectronics Corp