ADS5270IPFPT datasheet(21/31 Pages) TI1

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RESET

POWER-DOWN MODE

LAYOUT OF PCB WITH PowerPAD

CONNECTING HIGH-SPEED,

ADS5270

www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009

It is recommended that the isolation be maintained

onboard by using separate supplies to drive AVDD

After the supplies have stabilized, it is necessary to

and LVDD, as well as separate ground planes for

give the device an active RESET pulse. This results

AVSS and LVSS.

in all internal registers resetting to their default value

The use of LVDS buffers reduces the injected noise

of 0 (inactive). Without a reset, it is possible that

considerably,

compared

CMOS

buffers.

The

some registers may be in their non-default state on

current in the LVDS buffer is independent of the

power-up. This may cause the device to malfunction.

direction of switching. Also, the low output swing as

When a reset is active, the device outputs ‘0’ code on

well as the differential nature of the LVDS buffer

all channels. However, the LVDS output clocks are

results in low-noise coupling.

unaffected by reset.

THERMALLY-ENHANCED PACKAGES

The ADS5270 has a power-down pin, referred to as

PD. Pulling PD high causes the device to enter the

The ADS5270 is housed in an 80-lead PowerPAD

power-down mode. In this mode, the reference and

thermally-enhanced package. To make optimum use

clock circuitry, as well as all the channels, are

the

thermal

efficiencies

designed

into

the

powered down. Device power consumption drops to

PowerPAD package, the printed circuit board (PCB)

less than 100mW in this mode. In power-down mode,

must be designed with this technology in mind.

the internal buffers driving REFT and REFB are

Please refer to SLMA004 PowerPAD brief PowerPAD

tri-stated and their outputs are forced to a voltage

Made Easy (refer to our web site at www.ti.com),

roughly equal to half of the voltage on AVDD. Speed

which addresses the specific considerations required

of recovery from power-down mode depends on the

when integrating a PowerPAD package into a PCB

value of the external capacitance on the REFT and

design. For more detailed information, including

REFB pins. For capacitances on REFT and REFB less

thermal modeling and repair procedures, please see

than 1

µF, the reference voltages settle to within 1%

the

technical

brief

SLMA002,

PowerPAD

of their steady-state values in less than 500

µs.

Thermally-Enhanced Package (www.ti.com).

Individual channels can also be selectively powered

Interfacing High-Speed LVDS Outputs (SBOA104),

down by programming registers.

an application report discussing the design of a

The ADS5270 also has an internal circuit that

simple deserializer that can deserialize LVDS outputs

monitors the state of stopped clocks. If ADCLK is

up to 840Mbps, can also be found on the TI web site

stopped for longer than 300ns (or if it runs at a speed

(www.ti.com).

less than 3MHz), this monitoring circuit generates a

logic signal

that

puts

the

device

partial

power-down

state.

result,

the

power

MULTI-CHANNEL ADCs TO XILINX FPGAs

consumption of the device is reduced when ADCLK is

A separate application note (XAPP774) describing

stopped.

The

recovery

from

such

partial

how to connect TI's high-speed, multi-channel ADCs

power-down takes

approximately

100

µs; this is

with serial LVDS outputs to Xilinx FPGAs can be

described in Table 2.

downloaded

directly

from

the

Xilinx

web

site

(http://www.xilinx.com).

Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage

DESCRIPTION

TYP

REMARKS

Recovery from power-down mode (PD = 1 to PD = 0).

500

µs

Capacitors on REFT and REFB less than 1µF.

Recovery from momentary clock stoppage ( < 300ns).

µs

Recovery from extended clock stoppage ( > 300ns).

100

µs

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