ADC10461 datasheet(13/23 Pages) TI1

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ADC10461, ADC10462, ADC10464

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SNAS074E – JUNE 1999 – REVISED MARCH 2013

APPLICATIONS INFORMATION

MODES OF OPERATION

The ADC10461, ADC10462, and ADC10464 have two basic digital interface modes. Figure 4 and Figure 5 are

timing diagrams for the two modes. The ADC10462 and ADC10464 have input multiplexers that are controlled by

the logic levels on pins S0 and S1 when S/H goes low. Table 1 and Table 2 are truth tables showing how the

input channels are assigned.

Mode 1

In this mode, the S/H pin controls the start of conversion. S/H is pulled low for a minimum of 250 ns. This causes

the comparators in the “coarse” flash converter to become active. When S/H goes high, the result of the coarse

conversion is latched and the “fine” conversion begins. After 600 ns (typical), INT goes low, indicating that the

conversion results are latched and can be read by pulling RD low. Note that CS must be low to enable S/H or

RD. CS is internally “ANDed” with S/H and RD; the input voltage is sampled when CS and S/H are low, and data

is read when CS and RD are low. INT is reset high on the rising edge of RD.

Table 1. Input Multiplexer Programming ADC10464

Channel

VIN0

VIN1

VIN2

VIN3

Table 2. Input Multiplexer Programming ADC10462

Channel

VIN0

VIN1

Mode 2

In Mode 2, also called “RD mode”, the S/H and RD pins are tied together. A conversion is initiated by pulling both

pins low. The A/D converter samples the input voltage and causes the coarse comparators to become active. An

internal timer then terminates the coarse conversion and begins the fine conversion. 850 ns (typical) after S/H

and RD are pull low, INT goes low, indicating that the conversion is completed. Approximately 20 ns later the

data appearing on the TRI-STATE output pins will be valid. Note that data will appear on these pins throughout

the conversion, but until INT goes low the data at the output pins will be the result of the previous conversion.

REFERENCE CONSIDERATIONS

The ADC10461, ADC10462, and ADC10464 each have two reference inputs. These inputs, VREF+ and VREF−, are

fully differential and define the zero to full-scale range of the input signal. The reference inputs can be connected

to span the entire supply voltage range (VREF− = 0V, VREF+ = VCC) for ratiometric applications, or they can be

connected to different voltages (as long as they are between ground and VCC) when other input spans are

required.

Reducing the overall VREF span to less than 5V increases the sensitivity of the converter (e.g., if VREF = 2V, then

1 LSB = 1.953 mV). Note, however, that linearity and offset errors become larger when lower reference voltages

are used. See Typical Performance Characteristics for more information. For this reason, reference voltages less

than 2V are not recommended.

In most applications, VREF− will simply be connected to ground, but it is often useful to have an input span that is

offset from ground. This situation is easily accommodated by the reference configuration used in the ADC10461,

ADC10462, and ADC10464. VREF− can be connected to a voltage other than ground as long as the voltage

source connected to this pin is capable of sinking the converter's reference current (12.5 mA Max @ VREF = 5V).

If VREF− is connected to a voltage other than ground, bypass it with multiple capacitors.

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