74AC11646

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3STATE OUTPUTS

SCAS079A − JULY 1987 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

2−1

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

at 125

°C

description

The 74AC11646 consists of bus transceiver

circuits, D-type flip-flops, and control circuitry

arranged for multiplexed transmission of data

directly from the input bus or from the internal

registers. Data on the A or B bus is clocked

into the registers on the low-to-high transition of

the appropriate clock (CLKAB or CLKBA) input.

Figure 1 illustrates the four fundamental bus-

management functions that can be performed with

the 74AC11646.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),

A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.

The 74AC11646 is characterized for operation from − 40

°C to 85°C.

DW PACKAGE

(TOP VIEW)

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28

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OE

A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

DIR

CLKAB

SAB

B1

B2

B3

B4

B5

B6

B7

B8

CLKBA

SBA

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.