DAC7724UB datasheet(14/21 Pages) TI1

14 / 21 page

DAC7724, 7725

OUT = V REFL +

REFH –V REFL

()•N

4096

STATE OF

SELECTED

STATE OF

INPUT

ALL DAC

R/W

RESET

LDAC

REGISTERS

L(1)

LLL

H(2)

Transparent

LLLL

Transparent

Latched

Transparent

Latched

Transparent

Latched

Transparent

Latched

Readback

Latched

Readback

Latched

Readback

Latched

Readback

Latched

X(3)

NONE

(All Latched)

Transparent

NONE

(All Latched)

Latched

XXXX

ALL

Reset(4)

NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7724 resets to 800H, DAC7725 resets to 000H. When RESET rises, all registers

that are in their latched state retain the reset value.

TABLE I. DAC7724 and DAC7725 Control Logic Truth Table.

DIGITAL INTERFACE

Table I shows the basic control logic for the DAC7724/25.

Note that each internal register is level triggered and not

edge triggered. When the appropriate signal is LOW, the

HIGH, the digital word currently in the register is latched.

The first set of registers (the Input Registers) are triggered

via the A0, A1, R/W, and CS inputs. Only one of these

registers is transparent at any given time. The second set of

registers (the DAC Registers) are all transparent when LDAC

input is pulled LOW.

Each DAC can be updated independently by writing to the

appropriate Input Register and then updating the DAC

configured as always transparent by keeping LDAC LOW—

the DAC update will occur when the Input Register is

written.

The double buffered architecture is mainly designed so that

each DAC Input Register can be written at any time and then

all DAC output voltages updated simultaneously by pulling

LDAC LOW. It also allows a DAC Input Register to be

written to at any point and the DAC voltage to be synchro-

nously changed via a trigger signal connected to LDAC.

DIGITAL TIMING

Figure 4 and Table II provide detailed timing for the digital

interface of the DAC7724 and DAC7725.

DIGITAL INPUT CODING

The DAC7724 and DAC7725 input data is in straight binary

format. The output voltage is given by the following equa-

tion:

where N is the digital input code. This equation does not

include the effects of offset (zero-scale) errors.

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