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A8904SLP Datasheet(PDF) 8 Page - Allegro MicroSystems |
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A8904SLP Datasheet(HTML) 8 Page - Allegro MicroSystems |
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8 / 18 page ![]() 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Functional Description Overview of operation. Each electrical revolution contains six states that control the three half-bridge outputs. Optimized switching from state to state is achieved through the adaptive commutation circuitry. During any state, one output is high, one is low and the other is high impedance. The back- EMF at the high-impedance output is sensed and compared to the voltage of the centertap and when the two signals are equivalent, the FCOM signal toggles. A controlled delay is then introduced before the sequencer commutates into the next state. Linear current-mode control is employed to provide precision control of the motor speed while maintaining ex- tremely low electrical noise emissions. The speed control is realized through a frequency-locked loop that processes the sensed back-EMF signals from the stator phases to eventually produce a TACH signal. The TACH signal is then compared to the desired programmed speed, to produce an error. The error signal is then used to linearly control the current through the low-side DMOS power devices to obtain the correct speed. Alternative control schemes can be introduced, giving the user maximum flexibility and optimization for each application. An external tachometer signal applied to the SECTOR DATA input, along with the internal speed reference can be used for high-precision speed control. As another alternative, the user can introduce external speed control by driving the FILTER terminal directly. Start-up routines are inherent in the solution to guarantee reliable start-up. During start-up, a YANK feature allows rapid transition to the nominal operating condition on the FILTER terminal. This feature is also available when the external speed control is used. Dynamic braking can be introduced by either the external BRAKE terminal or through the brake bit in the serial port. A serial port allows the user to program various features and modes of operation, such as motor speed, internal or external speed control, internal or external speed reference, current limit, sleep mode, direction, charge current (for blanking pulse), motor poles, transconductance gain, and various diagnostic outputs. Full device protection is incorporated, including program- mable overcurrent limit, thermal shutdown, and undervoltage shutdown on the logic supply. Power outputs. The power outputs of the A8904 are n- channel DMOS transistors with a total source plus sink r DS(on) of typically 1 Ω. An internal charge pump provides a voltage rail above the load supply for driving the high-side DMOS gates. Intrinsic ground clamp and flyback diodes provide protection when switching inductive loads. These diodes will also rectify the motor back-EMF during power-down conditions. If neces- sary, a transient voltage supply can be provided, by connecting an external Schottky power diode or pass FET in series, between the power source and the load supply (V BB). This FET or diode effectively isolates the low impedance path through the power source. A filter capacitor is also required to ‘hold up’ the rectified signal, and is connected between the load supply and ground. Back-EMF sensing motor startup and running algorithm. The A8904 provides a complete self-contained back-EMF sensing, startup and running commutation scheme. A state machine with six states, (shown in the tables below for both forward and reverse direction) controls the three half- bridge outputs. In each state, one output is high (sourcing current), one low (sinking current), and one is OFF (high impedance or ‘Z’). Motor back-EMF is sensed at the output that is OFF. Sequencer State (forward direction) OUT A OUT B OUT C 1 High Z Low 2 High Low Z 3 Z Low High 4 Low Z High 5 Low High Z 6 Z High Low Sequencer State (reverse direction) OUT A OUT B OUT C 1 High Z Low 6 Z High Low 5 Low High Z 4 Low Z High 3 Z Low High 2 High Low Z At start-up, the outputs are always enabled in state 1. The back-EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The motor will then either step forward, step backward or remain stationary (if in a null-torque position). If the motor does not move during the initial start-up state, the outputs are commutated automatically by the start-up oscillator. When suitable back-EMF signals are detected, the start-up oscillator is overridden and the corresponding timing clock is generated, providing synchronous back-EMF commuta- tion. The start-up oscillator period is determined by t CST = (VCSTH - VCSTL) x CST / IST(charge) where C ST is the start-up capacitor. |
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