CDC2509C

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS620A − DECEMBER 1998 − REVISED DECEMBER 2004

1

POST OFFICE BOX 655303

this Device

DIMM Design Support Document Rev. 1.2

100 MHz is

±150 ps

Enhanced Performance

|100 ps|

Synchronous DRAM Applications

Five and One Bank of Four Outputs

Bank

to Synchronize the Outputs to the Clock

Input

description

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled

or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in

phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

The CDC2509C is characterized for operation from 0

°C to 85°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

 1998 − 2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLK

2Y0

2Y1

GND

GND

2Y2

2Y3

2G

FBIN

1

2

3

4

5

6

7

8

9

10

11

12

AGND

1Y0

1Y1

1Y2

GND

GND

1Y3

1Y4

1G

FBOUT

24

23

22

21

20

19

18

17

16

15

14

13

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