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B-69

U350

Hybrid Quad Silicon Junction Field-Effect Transistor Array

Reverse Gate Source & Reverse Gate Drain Voltage

– 25 V

Gate Current

25 mA

Continuous Device Power Dissipation

400 mW

Power Derating

3.2 mW/°C

TOÐ78 Package

Dimensions in Inches (mm)

Pin Configuration

1 Gate 1 & 3, 2 Drain 1 & 4,

3 Source 1 & 2, 4 Ground & Case,

5 Source 3 & 4, 6 Drain 2 & 3,

7 Gate 2 & 4, 8 Omitted

At 25°C free air temperature:

U350

Four Matched Process NJ72L

Static Electrical Characteristics

Min

Typ

Max

Unit

Test Conditions

Gate Source Breakdown Voltage

– 25

V

Gate Reverse Current

– 1

nA

– 1

µA

Gate Source Cutoff Voltage

– 2

– 6

V

Gate Source Forward Voltage

1V

Drain Saturation Current (Pulsed)

24

60

mA

Dynamic Electrical Characteristics

Drain Source ON Resistance

50

90

Ω

f = 1 kHz

Common Source

10

18

mS

f = 1 kHz

Forward Transconductance

Common Source Output Conductance

150

µS

f = 1 kHz

Drain Gate Capacitance

2.5

pF

f = 1 MHz

Gate Source Capacitance

5pF

f = 1 MHz

(Conversion Gain)

4dB

f = 100 MHz

Noise Figure

NF

7

dB

f = 100 MHz

Saturation Drain Current Ratio

0.9

1

Gate Source Cutoff Voltage Ratio

0.9

1

Common Source

0.9

1

f = 1 kHz

Forward Transconductance

Differential Output Conductance

0.9

1

f = 1 kHz

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Databook.fxp

1/13/99 2:09 PM

Page B-69