AD7266 datasheet(4/17 Pages) AD

4 / 17 page

AD7266

Preliminary Technical Data

Parameter

Specification

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH

VDRIVE – 0.2

V min

Output Low Voltage, VOL

0.4

V max

Floating State Leakage Current

±1

µA max

Floating State Output Capacitance3

pF max

Output Coding

Straight (Natural) Binary

SGL/DIFF = 1 with 0 V to VREF range selected

Twos Complement

SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range

CONVERSION RATE

Conversion Time

SCLK Cycles

437.5 ns with SCLK = 32 MHz

Track/Hold Acquisition Time3

100

ns max

Throughput Rate

MSPS max

POWER REQUIREMENTS

VDD

2.7/5.25

V min/V max

VDRIVE

2.7/5.25

V min/V max

IDD6

Digital I/Ps = 0 V or VDRIVE

Normal Mode (Static)

mA max

Operational, fs = 2 MSPS

mA max

VDD = 5 V

mA max

VDD = 3 V

Partial Power-Down Mode

TBD

mA max

fs = 200 kSPS

Partial Power-Down Mode

500

µA max

Static

Full Power-Down Mode

µA max

Power Dissipation6

Normal Mode (Operational)

mW max

VDD = 5 V

Partial Power-Down (Static)

2.5

mW max

VDD = 5 V

Full Power-Down (Static)

µW max

VDD = 5 V

NOTES

1 Temperature ranges as follows: -40°C to +125°C

2 See

section.

Terminology

3 Sample tested during initial release to ensure compliance.

4 Relates to Pins DCAPA or DCAPB.

5 See Reference section for DCAPA, DCAPB output impedances.

6 See Power Versus Throughput Rate section.

TIMING SPECIFICATIONS

Table 2. AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, TA = TMAX to TMIN, unless otherwise noted

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

kHz min

MHz max

tCONVERT

14 × tSCLK

ns max

tSCLK = 1/fSCLK

437.5

ns max

fSCLK = 32 MHz, VDD = 5 V, FSAMPLE = 2 MSPS

560

ns max

fSCLK = 25 MHz, VDD = 3 V, FSAMPLE = 1.5 MSPS

tQUIET

ns max

Minimum time between end of serial read and next falling edge of CS

ns min

CS to SCLK setup time

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

ns max

Data access time after SCLK falling edge.

0.4tSCLK

ns min

SCLK low pulse width

0.4tSCLK

ns min

SCLK high pulse width

ns min

SCLK to data valid hold time

ns max

CS rising edge to DOUTA, DOUTB, high impedance

ns min

CS rising edge to falling edge pulsewidth

t10

ns min

SCLK falling edge to DOUTA, DOUTB, high impedance

ns max

SCLK falling edge to DOUTA, DOUTB, high impedance

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.

Rev. PrG | Page 4 of 17

AD7266 Datasheet(PDF) 4 Page - Analog Devices

AD7266 Datasheet(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL