AD7266ASU datasheet(15/17 Pages) AD

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Preliminary Technical Data

AD7266

SERIAL INTERFACE

Figure 11 shows the detailed timing diagram for serial

interfacing to the AD7266. The serial clock provides the

conversion clock and controls the transfer of information from

the AD7266 during conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track and hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at this point. The conversion is also initiated at this point and

requires a minimum of 14 SCLKs to complete. Once 13 SCLK

falling edges have elapsed, the track-and-hold will go back into

track on the next SCLK rising edge, as shown in Figure 11 at

point B. If a 16 SCK transfer is used then 2 trailing zeros will

appear after the final LSB. On the rising edge of CS, the

conversion will be terminated and DOUTA and DOUTB will go

back into three-state. If CS is not brought high but is instead

held low for a further 14 (or 16) SCLK cycles on DOUTA, the data

from conversion B will be output on DOUTA (followed by 2

trailing zeros). Likewise, if CS is held low for a further 14 (or 16)

SCLK cycles on DOUTB, the data from conversion A will be

output on DOUTB. This is illustrated in Figure 12 where the case

for DOUTA is shown. Note that in this case, the DOUT line in use

will go back into three-state on the 32nd SCLK falling edge or

the rising edge of CS, whichever occurs first.

A minimum of fourteen serial clock cycles are required to

perform the conversion process and to access data from one

conversion on either data line of the AD7266. CS going low

provides the leading zero to be read in by the microcontroller or

DSP. The remaining data is then clocked out by subsequent

SCLK falling edges, beginning with a second leading zero. Thus

the first falling clock edge on the serial clock has the leading

zero provided and also clocks out the second leading zero. The

12 bit result then follows with the final bit in the data transfer

valid on the fourteenth falling edge, having being clocked out

on the previous (thirteenth) falling edge. In applications with a

slower SCLK, it may be possible to read in data on each SCLK

rising edge depending on the SCLK frequency used, i.e., the first

rising edge of SCLK after the CS falling edge would have the

leading zero provided and the thirteenth rising SCLK edge

would have DB0 provided.

SCLK

DOUTA

DOUTB

2 Leading Zeros

3-STATE

tquiet

3-STATE

DB11

DB10

DB2

DB0

DB1

DB9

DB8

Figure 11 Serial Interface Timing Diagram

SCLK

DOUTA

3-STATE

ZERO

DB11B

2 Leading Zeros,

t10

DB11A

2 Leading

Zeros,

DB10A

DB9A

ZERO

2 Traiing Zeros,

ZERO

2 Traiing Zeros,

Figure 12. Reading data from Both ADCs on One DOUT Line with 32 SCLKs

Rev. PrG | Page 15 of 17

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