CP3SP33SMSSLASHNOPB datasheet(46/407 Pages) TI1

Part #	CP3SP33SMS/NOPB

Description	Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces

PDF	407 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

Logo

46 / 407 page

XCSn

HCLK

DS415

XAn

XWE

XBEn

XDn

Data

Address

tAS

tWR

tWP

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 10-2 shows the timing of a write cycle on the external memory bus.

Figure 10-2. Write Cycle Timing

An 8-level write buffer allows the EBIU to accept a write cycle and release the bus master (CPU, DSP, or

one of the DMA controllers) to continue execution without waiting for the write data to propagate to

external memory.

A read cycle is not allowed to propagate to external memory while there are any writes pending in the

write buffer. The read cycle is stalled until the write buffer has been flushed to memory. This mechanism

enforces memory coherency when the target of a read is modified by a pending write. In some cases,

software performance can be optimized by grouping writes together (for example, by loop unrolling) to

avoid alternating between reads and writes.

External Bus Interface Unit

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 46 Page - Texas Instruments