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HD3SS460RHRT Datasheet(PDF) 21 Page - Texas Instruments

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Part # HD3SS460RHRT
Description  4 x 6 Channels USB Type-C Alternate Mode MUX
PDF  34 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

HD3SS460RHRT Datasheet(HTML) 21 Page - Texas Instruments

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ESD Components
Place in pass through manner with no stub
CTX1N
CTX1P
CRX1N
CRX1P
CRX2P
CRX2N
CTX2N
CTX2P
USB2_N0
USB2_P0
CC2
CC1
CSBU1
CSBU2
U12
TPD6E05U06
NC2
2
NC1
1
NC3
3
NC4
4
GND
5
GND
10
D2-
11
D2+
12
D1-
13
D1+
14
NC5
6
NC6
7
D3-
8
D3+
9
U8
TPD4E05U06
D1+
1
D1-
2
GND
3
D2+
4
D2-
5
NC6
6
NC7
7
GND
8
NC9
9
NC10
10
U9
TPD4E05U06
D1+
1
D1-
2
GND
3
D2+
4
D2-
5
NC6
6
NC7
7
GND
8
NC9
9
NC10
10
USB2_N0
USB2_P0
CSBU1
CSBU2
Copyright © 2016, Texas Instruments Incorporated
TypeC Connector and Pin Mapping
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VBUS
ML2P
ML2N
ML1P
ML1N
ML3P
ML3N
ML0P
ML0N
ML1N
ML1P
ML2N
ML2P
ML0N
ML0P
ML3N
ML3P
GND
A11
A12
SSRXP1
SSRXP2
SSRXN1
SSRXN1
B9
B8
B7
B6
B5
B4
B3
B2
B1
AUXP
DN1
SBU2
GND
VBUS
B12
B11
B10
CC1
GND
AUXP
DP1
DN1
AUXN
SBU1
VBUS
SSTXP1
SSTXP2
SSTXN1
SSTXN2
SSRXP2
SSRXP1
SSRXN2
SSRXN1
AUXN
DP1
SSTXP2
SSTXP1
SSTXN2
SSTXN1
GND
VBUS
CC2
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
pull-down
resistor
between 1M-2M
is
recommended
on SBU1 and
SBU2.
CC1
CC2
CRX1P
CRX1N
CTX1P
CTX1N
CRX2N
CRX2P
CTX2N
CTX2P
CSBU1
CSBU2
USB2_N0
USB2_P0
CSBU1
CSBU2
VBUS
CC1
pg3
CC2
pg3
C8
10uF
J2
USB_TypeC_Receptacle_
GND0
A1
SSTXP1
A2
SSTXN1
A3
VBUS1
A4
CC1
A5
DP1
A6
DN1
A7
SBU1
A8
VBUS2
A9
SSRXN2
A10
SSRXP2
A11
GND1
A12
GND2
B1
SSTXP2
B2
SSTXN2
B3
VBUS3
B4
CC2
B5
DP2
B6
DN2
B7
SBU2
B8
VBUS4
B9
SSRXN1
B10
SSRXP1
B11
GND3
B12
Shield1
g1
Shield2
g2
Shield3
g3
Shield4
g4
Shield5
g5
Shield6
g6
R158
2M
R156
2M
Copyright © 2016, Texas Instruments Incorporated
21
HD3SS460
www.ti.com
SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
Product Folder Links: HD3SS460
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Figure 17. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (1 of 3)
Figure 18. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (2 of 3)



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