Time (400 ns/DIV)

0 V

Time (400 ns/DIV)

0 V

DS8921, DS8921A, DS8921AT

SNLS374D – MAY 1998 – REVISED JANUARY 2015

www.ti.com

Typical Application (continued)

9.2.1 Design Requirements

•

Apply TTL or LVCMOS signal to driver input at DI

•

Transmit complementary outputs at DO+ and DO-

•

Receive complimentary input signals at RI+ and RI-

•

Receive TTL output signal at RO

•

Use controlled-impedance transmission lines such as printed circuit board traces, twisted-pair wires or parallel

wire cable

•

Place terminating resistor at the far end of the differential pair

9.2.2 Detailed Design Procedure

•

Connect VCC and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass

capacitor

•

Use TTL/LVCMOS logic levels at DI and RO

•

Use controlled-impedance transmission media for the differential signals DI+- and RO+-

•

Place a terminating resistor at the far-end of the differential pair to avoid reflection

•

Ensure the received complimentary signals at RO+ and RO- are within the signal threshold of ±200 mV

9.2.3 Application Curves

2.0 Mbps Single-Ended 1010 Data Pattern

2.0 Mbps Differential Data Pattern

Note: The input for the driver is Figure 12

Figure 12. Driver Single-Ended Input Signal

Figure 13. Driver Differential Output Signal

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