ADS7871

SLAS370C − APRIL 2002 − REVISED OCTOBER 2004

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13

Reg.7 D5

OSCR = 1

Reg.7 D5

OSCR = 0

1/4

Internal

Reference

Enabled by

Reg.7D3,

REFE

Enabled by

Reg.7 D2,

BUFE

REF

BUF

Internal Control

Logic

DCLK

N Set by

Reg.3 D[1:0],

CFD[1:0]

1/N Divider

Enabled by

Pin 18 OSC Enable

Reg.7 D4, OSCE

Enabled by

Reg.7 D4, OSCE or

Reg.7D5, OSCR or

Pin 18, OSC Enable

Internal Oscillator

(2.5 MHz)

OSC CLK

To ADC

Pin 18

OSC

ENABLE

Pin 19

CCLK

Pin 27

BUFIN

Pin 26

VREF

ADS7871

Pin 28

BUFOUT/REFIN

Figure 15. Block Diagram With Internal and External Clocks and References

Voltage Reference and Buffer Amplifier

The ADS7871 uses a patented switched capacitor implementation of a band-gap reference. The circuit has

curvature correction for drift and can be software configured for output voltages of 1.15 V, 2.048 V, or 2.5 V

(default). The internal reference output (VREF) is not designed to drive a typical load; a separate buffer amplifier

must be used to supply any load current.

The internal reference buffer (REFBUF) can source many tens of milliamps to quickly charge a filter capacitor

tied to its output, but it can only typically sink 200

µA. If there is any significant noise on the REFIN pin, then

a resistor to ground (

≥ 250 Ω) would improve the buffers ability to recover from a positive going noise spike.

This would, of course, be at the expense of power dissipation.

The temperature compensation of the onboard reference is adjusted with the reference buffer in the circuit.

Performance is specified in this configuration.

Programmable Gain Amplifier

The programmable gain amplifier (PGA) provides gains of 1, 2, 4, 5, 8, 10, 16, and 20 V/V. The PGA is a single

supply, rail-to-rail input, auto-zeroed, capacitor based instrumentation amplifier. PGA gain is set by bits G2

through G0 of register 4.

The ability to detect when the PGA outputs are driven to clipping, or nonlinear operation, is provided by the least

significant bit of the output data (register 0) being set to one. This result is the logical OR of fault detecting

comparators within the ADS7871 monitoring the outputs of the PGA. The inputs are also monitored, for

problems, often due to ac common mode or low supply operation and ORed to this OVL bit. Register 2 can be

read to determine what fault conditions existed during the conversion. An illustration of how the OVL bit could

be set without having reached the maximum output code of the A/D converter is shown in Figure 10. The OVL

bit also facilitates a quick test to allow for an auto-ranging application, indicating to the system controller it should

try reducing the PGA gain.