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DP83916 Datasheet(PDF) 58 Page - National Semiconductor (TI) |
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DP83916 Datasheet(HTML) 58 Page - National Semiconductor (TI) |
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58 / 96 page  50 Bus Interface (Continued) 5453 Memory Cycle for BMODE e 1 Asynchronous Mode On the rising edge of T1 the SONIC-16 asserts ECS to indicate that the memory cycle is starting The address (A23 – A1) bus status (S2 – S0) and the direction strobe (MRW) are driven and do not change for the remainder of the memory cycle On the falling edge of T1 the SONIC-16 deasserts ECS and asserts AS In asynchronous mode DSACK01 are asynchronously sampled on the falling edge of both T1 and T2 DSACK01 do not need to be synchronized to the bus clock because the chip always resolves these signals to either a high or low state If a synchronous termination of the bus cycle is required however STERM may be used STERM is sam- pled on the rising edge of T2 and must meet the setup and hold times with respect to that edge for proper operation Meeting the setup time for DSACK01 or STERM guaran- tees that the SONIC-16 will terminate the memory cycle 1 TLF11722 – 36 FIGURE 5-10 Memory Read BMODEe1 Asynchronous (1 Wait-State) TLF11722 – 37 FIGURE 5-11 Memory Read BMODEe1 Asynchronous (2 Wait-State) 58 |
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