ADS8341

12

SBAS136D

FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated

serial port.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8341 will operate with a reference in the range of

difference between the +IN input and the –IN input, see

Figure 2. For example, in the single-ended mode, a 1.25V

reference, with the COM pin grounded, the selected input

channel (CH0 - CH3) will properly digitize a signal in the

range of 0V to 1.25V. If the COM pin is connected to 0.5V,

the input range on the selected channel is 0.5V to 1.75V.

There are several critical items concerning the reference

input and its wide voltage range. As the reference voltage is

reduced, the analog voltage weight of each digital output

code is also reduced. This is often referred to as the LSB

(least significant bit) size and is equal to the reference

voltage divided by 65,536. Any offset or gain error inherent

in the A/D converter will appear to increase, in terms of LSB

size, as the reference voltage is reduced. For example, if the

offset of a given converter is 2LSBs with a 2.5V reference,

then it will typically be 10LSBs with a 0.5V reference. In

each case, the actual offset of the device is the same, 76

µV.

Likewise, the noise or uncertainty of the digitized output will

increase with lower LSB size. With a reference voltage of

500mV, the LSB size is 7.6

µV. This level is below the

internal noise of the device. As a result, the digital output

code will not be stable and vary around a mean value by a

number of LSBs. The distribution of output codes will be

gaussian and the noise can be reduced by simply averaging

consecutive conversion results or applying a digital filter.

With a lower reference voltage, care should be taken to

provide a clean layout including adequate bypassing, a clean

(low-noise, low-ripple) power supply, a low-noise reference,

and a low-noise input signal. Because the LSB size is lower,

the converter will also be more sensitive to nearby digital

signals and electromagnetic interference.

drives the Capacitor Digital-to-Analog Converter (CDAC)

portion of the ADS8341. Typically, the input current is

13

µA with a 2.5V reference. This value will vary by

microamps depending on the result of the conversion. The

reference current diminishes directly with both conversion

rate and reference voltage. As the current from the reference

is drawn on each bit decision, clocking the converter more

quickly during a given conversion period will not reduce

overall current drain from the reference.

DIGITAL INTERFACE

Figure 3 shows the typical operation of the ADS8341’s

digital interface. This diagram assumes that the source of the

digital signals is a microcontroller or digital signal processor

with a basic serial interface (note that the digital inputs are

communication between the processor and the converter

consists of eight clock cycles. One complete conversion can

be accomplished with three serial communications, for a

total of 24 clock cycles on the DCLK input.

The first eight cycles are used to provide the control byte via

the DIN pin. When the converter has enough information

about the following conversion to set the input multiplexer

appropriately, it enters the acquisition (sample) mode. After

three more clock cycles, the control byte is complete and the

converter enters the conversion mode. At this point, the

input sample-and-hold goes into the hold mode. The next 16

clock cycles accomplish the actual analog-to-digital conver-

sion.

Control Byte

Also shown in Figure 3 is the placement and order of the

control bits within the control byte. Tables III and IV give

detailed information about these bits. The first bit, the ‘S’

bit, must always be HIGH and indicates the start of the

control byte. The ADS8341 will ignore inputs on the DIN

pin until the start bit is detected. The next three bits (A2 -

A0) select the active input channel or channels of the input

multiplexer (see Tables I and II and Figure 2).

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

S

A2A1A0

—

SGL/DIF

PD1

PD0

TABLE III. Order of the Control Bits in the Control Byte.

t

ACQ

Acquire

Idle

Conversion

1

DCLK

CS

81

15

DOUT

BUSY

(MSB)

(START)

(LSB)

A2

S

DIN

A1

A0

SGL/

DIF

PD1 PD0

14

13

12

11

10

9

8

7654321

0

Zero Filled...

81

8

Acquire

Idle

Conversion

18

1

15

(MSB)

(START)

A2

SA1

A0

SGL/

DIF

PD1 PD0

14