LM113QML datasheet(2/10 Pages) TI1

2 / 10 page

LM113QML, LM113QML-SP

SNVS367A – DECEMBER 2010 – REVISED APRIL 2013

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Schematic Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1)

Power Dissipation(2)

100 mW

Reverse Current

50 mA

Forward Current

50 mA

Storage Temperature Range

−65°C ≤ TA ≤ +150°C

Lead Temperature (Soldering, 10 seconds)

300°C

Maximum Junction Temperature (TJmax)

+150°C

Operating Temperature Range

−55°C ≤ TA ≤ +125°C

Thermal Resistance

θJA

TO (Still Air)

440°C/W

TO (500LF / Min Air Flow)

TBD

CFP (Still Air)

218°C/W

CFP (500LF / Min Air Flow)

140°C/W

θJC

80°C/W

CFP

27°C/W

Package Weight

275mg

CFP

220mg

ESD Tolerance(3)

4000V

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. Theensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2)

The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),

θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any

temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.

(3)

Human body model, 1.5K

Ω in series with 100pF.

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